Instructor
Bevan Baas
Office hours
Mon 4:00–5:00pm
Tue 10:20am after lecture
Th 10:20am after lecture
Lecture
TTh 9:00–10:20pm
Prerequisites: EEC 150B, EEC 170, and EEC 180; or consent of instructor
Catalog description
Digital signal processors, building blocks, and algorithms. Design and implementation of processor algorithms, architectures, control, functional units, and circuit topologies for increased performance and reduced circuit size and power dissipation.
Goals: Through this course, students will develop the necessary skills to design simple synthesizable processors suitable for numerically intensive processing with an emphasis on small chip area and high-performance. Secondly, students will learn to design processors for simple digital signal processing tasks through the simultaneous design of DSP algorithms, processor architectures, and hardware design.
Grading
Quizzes cover material through the end of the previous lecture with a general emphasis on more recent material. You may bring one page of double-sided hand-written (no photocopying) notes to the quizzes.
Other references
Read by | Paper | Comments |
Th, Jan 7 | Programmable DSP Architectures: Part I, Edward A. Lee, ASSP Magazine, October 1988. | Easy to read article on the most notable features of programmable DSP processors. These first-generation DSP processors were more clearly distinguished from general-purpose processors than they are today. Note the publication date of 1988—many of the technical specifications are impressive only when considered in the context of the technology available at that time. |
Reference | Programmable DSP Architectures: Part II, Edward A. Lee, ASSP Magazine, January 1989. | Easy to read article presenting an overview of issues of programming pipelined DSP processors with complex organizations. |
When needed |
Notes on ECE Machines and Tool Setup
Notes on a few useful linux commands Notes on Common Problems on ECE Machines Make Frequent Backups of Your Work |
Notes on ECE linux machines and your CAD tool environment setup
Notes on a few useful linux commands |
When needed |
verilog: notes to run it verilog: common pitfalls with suggestions verilog: example code |
Notes on running ncverilog here at UC Davis |
When needed |
Quick Reference For Verilog,
R. Madhavan
[2up]
Verilog Quick Reference Guide, S. Sutherland, skim it |
A very helpful and handy verilog reference.
Convenient and very nicely presented. Note that it covers aspects of verilog that shouldn't be used for sythesizable code such as signal strengths and primitives. [original] |
When needed | Notes on running Design CompilerFEB 8 |
Notes and starter files for Synopsys' Design Compiler, and details on our standard cell library |
Reference | A Signed Binary Multiplication Technique, A. D. Booth, Quarterly Journal of Mechanics and Applied Mathematics, June 1951. | Classic paper introduces the Booth Algorithm. |
Reference | High-speed Arithmetic in Binary Computers, O. L. MacSorley, Proceedings of the IRE, January 1961. | Classic paper that introduces the Modified Booth's Algorithm which is commonly used in hardware implementations. |
When assigned | SPIM: A Pipelined 64 x 64-bit Iterative Multiplier, M. Santoro and M. Horowitz, IEEE Journal of Solid-State Circuits, April 1989. | Classic paper is that apparently the first to describe the 4:2 adder. It certainly contributed to the popular use of the 4:2 and its use in adding multiplier partial products. |
When needed |
matlab: notes for
running matlab: tips for 281 |
Notes for running matlab here at UC Davis, and some functions and examples |
Th, Feb 18 Skim. |
An Algorithm for the Machine Calculation of Complex Fourier Series, James W. Cooley and John W. Tukey, Mathematics of Computation, April 1965. | The paper that popularized FFTs. |
Th, Feb 18 Skim. |
Historical Notes on the Fast Fourier Transform, James W. Cooley, Peter A. W. Lewis, and Peter D. Welch; Proceedings of the IEEE, October 1967. | Some notes on FFT history 2 years after the seminal Cooley & Tukey paper. |
Reference | Trends in Multicore DSP Platforms, Karam, AlKamal, Gatherer, Frantz, Anderson, Evans, IEEE Signal Processing Magazine, November 2009. | A paper with a thorough and detailed survey of modern multicore DSP processors |
Number | Due Date | % Hwk/proj grade | Material covered |
1 |
Mon, Jan 25, 5:00 pm | 25% | Binary arithmetic and conversion, verilog, and many-input adders |
2 |
Fri, Feb 5, 5:00 pm | 15% | Synthesis, adders, pipelining |
3 |
Mon, Feb 22, 5:00 pm | 20% | Digital filter tools, design, and optimization |
4 |
Tue, March 16, 5:00 pm | 40% | Convolutional neural net engine |
All work for a particular hwk/project must be submitted at one time.
If an assignment is reviewed in class, no credit is possible for late work. If an assignment was not reviewed in class, there will be a 1/3 reduction of remaining credit per day (i.e., 100% → 67% → 44% → 30% ...).
Normally late work can not be accepted after its deadline however if a serious issue such as an illness prevents you from completing work on time, obtain a verifiable written excuse, bring it to the instructor, and something will be worked out.
To request a regrade, submit: 1) a short description of the suspected grading error, 2) the following statement on your regrade request with your signature immediately below it: "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct."
Date | Lecture | Handouts | Topics |
Tue, January 5 |
1 |
Lecture 1 Course Introduction Key attributes of DSP processors Seven basic diagramsMAR 15 |
Course introduction DSP overview Seven basic diagrams, |
Th, January 7 | 2 |
Lecture 2 Chip design methodologies |
Chip design methodologies, Multiply-accumulate, FIR, convolution, dot products Quantization noise and word size |
Tue, January 12 | 3 |
Lecture 3 Quantization Noise and Word Size Sign Extension Floating Point |
Number representations: fixed-pt integer: unsigned, signed Sign extension for 2's complement Number representations: fixed-pt fractional Number representations: Floating point |
Th, January 14 |
4 |
Lecture 4 |
Number representations: Block floating point Number representations: Redundant (carry-save) 3:2 and 4:2 carry-save adders Fast carry-save addition |
Tue, January 19 |
5 |
Lecture 5 Float-Fixed conversion Verilog 1: Overview Verilog 2: Language basics Verilog 3: Time and delay Verilog 4: Common mistakes Verilog 5: Testing Verilog 6: Decoder example Adders & subtractors Adders: Efficient Multiple Input |
Floating pt to fixed pt conversion Verilog Overview Verilog Language basics Verilog Time and delay Verilog Common mistakes Verilog Hardware vs. testing Verilog decoder examples Adders & subtractors Adders: multiple-input I |
Th, January 21 | 6 |
Lecture 6 Adders: Faster CPAs Flip-flops and registers |
Adders: multiple-input II Adders: faster carry-propagate Carry-Select adders Carry-Lookahead adders FFs, registers, and The 9 Rules I |
Tue, January 26 Quiz 1 (zoom instructions) |
7 |
Lecture 7 |
FFs, registers, and The 9 Rules II |
Th, January 28 | 8 |
Lecture 8 SynthesisFEB 8; Slides 149,151,157 |
FFs, registers, and The 9 Rules III Synthesis |
Tue, February 2 |
9 |
Lecture 9 Clocks Critical timing relationships MultipliersMAR 1; Slides 185,190 Booth encoding |
Clocks Critical timing relationships (review) Multipliers Booth encoding of multipliers Read Santoro paper |
Th, February 4 |
10 |
Lecture 10 Example Multiplier Squaring Fixed Input Multiplication dB |
Example multiplier Squaring Fixed-input multiplication dB |
Tue, February 9 | 11 |
Lecture 11 Digital Filter Coefficient Design Estimating Spectral MagnitudeFEB 9 |
Digital filters Digital filter coefficient design Seeing the freq. response of filters Estimating spectral magnitude of signals |
Th, February 11 | 12 |
Lecture 12 FIR hardwareFEB 22 Saturation |
FIR scaling Saturation I |
Tue, February 16 Quiz 2 (zoom instructions) |
13 |
Lecture 13 Rounding |
Saturation II Compression Rounding I |
Th, February 18 |
14 |
Lecture 14 Drive Through Processing Complex ArithmeticFEB 23; Slide 193 |
Rounding II Drive through processing Complex addition, multiplication, rotation, format conversion |
Tue, February 23 |
15 |
Lecture 15 Complex Signal Magnitude Estimation Multiplier Scaling |
Complex magnitude estimation Multiplication scaling |
Th, February 25 |
16 |
Lecture 16 Control and counters FSMsFEB 25 Gen Complex Functions |
Control circuits, state machine design Generating complex functions |
Tue, March 2 | 17 |
Lecture 17 Memories |
Memories: structure, types (6T SRAM, multi-port SRAM, ROM, DRAM) Memory uses in standard-cell ASIC designs |
Th, March 4 |
18 |
Lecture 18 Signals in Time and Frequency DFT & FFT Background |
Signals in time and frequency Discrete Fourier transform (DFT) fast Fourier transform (FFT) |
Tue, March 9 |
19 |
Lecture 19 FFT Algorithms Multi-rate signal processing downsamp_movie.m Nyquist Filters Viterbi Decoding |
FFT processor architectures Multi-rate processing Upsampling, decimation Nyquist filters Nyquist filters with upsampling Viterbi decoders |
Th, March 11 Quiz 3 (zoom instructions) |
20 |
Ref:Variable-freq clocking HW Ref:The RRI FFT Ref:Multiple Access Ref:DSSS Ref:DSSS Spreadsheet |
I. Digital signal processing overview A. DSP workloads B. Example applications C. Programmable processors II. Processor building blocks A. Verilog hardware description language B. Binary number representations C. Carry-propagate adders D. Carry-save adders E. Multipliers F. Fixed-input multipliers G. Complex arithmetic hardware H. Memories III. DSP algorithms and systems A. FIR filtering B. Processor control and datapath integration C. Multi-rate signal processing D. Example systems: FFT, Viterbi, DSSS, CDMA,. IV. Design optimization A. Verilog synthesis to a gate netlist B. Delay estimation and reduction C. Area estimation and reduction D. Power estimation and reduction