EEC 281 - VLSI Digital Signal Processing
Winter 2021

Course Information

Course Readings

Read by Paper Comments
Th, Jan 7 Programmable DSP Architectures: Part I, Edward A. Lee, ASSP Magazine, October 1988. Easy to read article on the most notable features of programmable DSP processors. These first-generation DSP processors were more clearly distinguished from general-purpose processors than they are today. Note the publication date of 1988—many of the technical specifications are impressive only when considered in the context of the technology available at that time.
Reference Programmable DSP Architectures: Part II, Edward A. Lee, ASSP Magazine, January 1989. Easy to read article presenting an overview of issues of programming pipelined DSP processors with complex organizations.
When needed Notes on ECE Machines and Tool Setup
Notes on a few useful linux commands
Notes on Common Problems on ECE Machines
Make Frequent Backups of Your Work
Notes on ECE linux machines and your CAD tool environment setup
Notes on a few useful linux commands
When needed verilog: notes to run it
verilog: common pitfalls with suggestions
verilog: example code
Notes on running ncverilog here at UC Davis
When needed Quick Reference For Verilog, R. Madhavan [2up]
Verilog Quick Reference Guide, S. Sutherland, skim it
A very helpful and handy verilog reference.
Convenient and very nicely presented. Note that it covers aspects of verilog that shouldn't be used for sythesizable code such as signal strengths and primitives. [original]
When needed Notes on running Design CompilerFEB 8

Notes and starter files for Synopsys' Design Compiler, and details on our standard cell library
Reference A Signed Binary Multiplication Technique, A. D. Booth, Quarterly Journal of Mechanics and Applied Mathematics, June 1951. Classic paper introduces the Booth Algorithm.
Reference High-speed Arithmetic in Binary Computers, O. L. MacSorley, Proceedings of the IRE, January 1961. Classic paper that introduces the Modified Booth's Algorithm which is commonly used in hardware implementations.
When assigned SPIM: A Pipelined 64 x 64-bit Iterative Multiplier, M. Santoro and M. Horowitz, IEEE Journal of Solid-State Circuits, April 1989. Classic paper is that apparently the first to describe the 4:2 adder. It certainly contributed to the popular use of the 4:2 and its use in adding multiplier partial products.
When needed matlab: notes for running
matlab: tips for 281
Notes for running matlab here at UC Davis, and some functions and examples
Th, Feb 18
An Algorithm for the Machine Calculation of Complex Fourier Series, James W. Cooley and John W. Tukey, Mathematics of Computation, April 1965. The paper that popularized FFTs.
Th, Feb 18
Historical Notes on the Fast Fourier Transform, James W. Cooley, Peter A. W. Lewis, and Peter D. Welch; Proceedings of the IEEE, October 1967. Some notes on FFT history 2 years after the seminal Cooley & Tukey paper.
Reference Trends in Multicore DSP Platforms, Karam, AlKamal, Gatherer, Frantz, Anderson, Evans, IEEE Signal Processing Magazine, November 2009. A paper with a thorough and detailed survey of modern multicore DSP processors

Homework / Projects

Course Topics, Slides, Notes, and Handouts

Future details are tentative. Some slides will be updated during the quarter and marked .

Date Lecture Handouts Topics
Tue, January 5
1 Lecture 1
Course Introduction
Key attributes of DSP processors
Seven basic diagramsMAR 15
Course introduction
DSP overview
Seven basic diagrams,
Th, January 7 2 Lecture 2
Chip design methodologies
Chip design methodologies,
FIR, convolution, dot products
Quantization noise and word size
Tue, January 12 3 Lecture 3
Quantization Noise and Word Size
Sign Extension
Floating Point
Number representations: fixed-pt integer: unsigned, signed
Sign extension for 2's complement
Number representations: fixed-pt fractional
Number representations: Floating point
Th, January 14
4 Lecture 4
Number representations: Block floating point
Number representations: Redundant (carry-save)
3:2 and 4:2 carry-save adders
Fast carry-save addition
Tue, January 19
5 Lecture 5
Float-Fixed conversion
Verilog 1: Overview
Verilog 2: Language basics
Verilog 3: Time and delay
Verilog 4: Common mistakes
Verilog 5: Testing
Verilog 6: Decoder example
Adders & subtractors
Adders: Efficient Multiple Input
Floating pt to fixed pt conversion
Verilog Overview
Verilog Language basics
Verilog Time and delay
Verilog Common mistakes
Verilog Hardware vs. testing
Verilog decoder examples
Adders & subtractors
Adders: multiple-input I
Th, January 21 6 Lecture 6
Adders: Faster CPAs
Flip-flops and registers
Adders: multiple-input II
Adders: faster carry-propagate
Carry-Select adders
Carry-Lookahead adders
FFs, registers, and The 9 Rules I
  Tue, January 26
Quiz 1
(zoom instructions)
7 Lecture 7
FFs, registers, and The 9 Rules II
Th, January 28 8 Lecture 8
SynthesisFEB 8; Slides 149,151,157
FFs, registers, and The 9 Rules III
Tue, February 2
9 Lecture 9
Critical timing relationships
MultipliersMAR 1; Slides 185,190
Booth encoding
Critical timing relationships (review)
Booth encoding of multipliers
Read Santoro paper
Th, February 4
10 Lecture 10
Example Multiplier
Fixed Input Multiplication
Example multiplier
Fixed-input multiplication
  Tue, February 9 11 Lecture 11
Digital Filter Coefficient Design
Estimating Spectral MagnitudeFEB 9
Digital filters
Digital filter coefficient design
Seeing the freq. response of filters
Estimating spectral magnitude of signals
Th, February 11 12 Lecture 12
FIR hardwareFEB 22
FIR scaling
Saturation I
Tue, February 16
Quiz 2
(zoom instructions)
13 Lecture 13
Saturation II
Rounding I
Th, February 18
14 Lecture 14
Drive Through Processing
Complex ArithmeticFEB 23; Slide 193
Rounding II
Drive through processing
Complex addition, multiplication, rotation, format conversion
Tue, February 23
15 Lecture 15
Complex Signal Magnitude Estimation
Multiplier Scaling
Complex magnitude estimation
Multiplication scaling
Th, February 25
16 Lecture 16
Control and counters
Gen Complex Functions
Control circuits, state machine design
Generating complex functions
Tue, March 2 17 Lecture 17
Memories: structure, types (6T SRAM, multi-port SRAM, ROM, DRAM)
Memory uses in standard-cell ASIC designs
Th, March 4
18 Lecture 18
Signals in Time and Frequency
DFT & FFT Background
Signals in time and frequency
Discrete Fourier transform (DFT)
fast Fourier transform (FFT)
Tue, March 9
19 Lecture 19
FFT Algorithms
Multi-rate signal processing
Nyquist Filters
Viterbi Decoding
FFT processor architectures
Multi-rate processing
Upsampling, decimation
Nyquist filters
Nyquist filters with upsampling
Viterbi decoders
Th, March 11
Quiz 3
(zoom instructions)
20 Ref:Variable-freq clocking HW
Ref:Multiple Access
Ref:DSSS Spreadsheet

Topical Outline

I.      Digital signal processing overview
        A.      DSP workloads
        B.      Example applications  
        C.      Programmable processors
II.     Processor building blocks
        A.      Verilog hardware description language
        B.      Binary number representations
        C.      Carry-propagate adders
        D.      Carry-save adders
        E.      Multipliers
        F.      Fixed-input multipliers
        G.      Complex arithmetic hardware
        H.      Memories
III.    DSP algorithms and systems
        A.      FIR filtering
        B.      Processor control and datapath integration
        C.      Multi-rate signal processing
        D.      Example systems: FFT, Viterbi, DSSS, CDMA,.
IV.     Design optimization
        A.      Verilog synthesis to a gate netlist
        B.      Delay estimation and reduction
        C.      Area estimation and reduction
        D.      Power estimation and reduction

Last update: March 16, 2021