EEC 281 - VLSI Digital Signal Processing
Winter 2022

Course Information

• Instructor
  Bevan Baas

• Office hours
  Mon 4:00–5:00pm
  Tue 10:20am after lecture
  Th 10:20am after lecture
  Fri 10:00am–11:00am (Tony Tsoi)

• Lecture
  TTh 9:00–10:20pm

• Prerequisites: EEC 150B, EEC 170, and EEC 180; or consent of instructor

• Catalog description

  Digital signal processors, building blocks, and algorithms. Design and implementation of processor algorithms, architectures, control, functional units, and circuit topologies for increased performance and reduced circuit size and power dissipation.

  Goals: Through this course, students will develop the necessary skills to design simple synthesizable processors suitable for numerically intensive processing with an emphasis on small chip area and high-performance. Secondly, students will learn to design processors for simple digital signal processing tasks through the simultaneous design of DSP algorithms, processor architectures, and hardware design.

• Grading

  • 55%   Homework/Projects (4)
  • 45%   Quizzes (3)

  Quizzes cover material through the end of the previous lecture with a general emphasis on more recent material. You may bring one page of double-sided hand-written (no photocopying) notes to the quizzes.

• Textbook: None required to purchase.

• Suggested references
  • Fundamentals of Digital Logic, with Verilog Design, Stephen Brown and Zvonko Vranesic. McGraw-Hill, 2003. Good overview of digital system design and many major building blocks with helpful verilog examples.

  • Computer Architecture, A Quantitative Approach, John Hennessy and David Patterson. Morgan Kaufmann, third edition, 2003. Probably the best reference for processor architectures. You should know this material already, so re-read material if you are rusty.

  • Getting Started with Matlab, Rudra Pratap. Oxford University Press, 2002. If you need a little help learning matlab, buy and read this. Chapter 2 has some nice tutorials, chapter 3 summarizes basic functions and file I/O, chapter 4 covers scripts, and chapter 6 gives a good overview of graphing. Concise with good coverage. $30 on amazon

  • Discrete-time Signal Processing, Oppenheim and Schaefer. Excellent reference for discrete-time systems, filtering, DFT, and other DSP algorithms.

  • Theory and Application of Digital Signal Processing, Rabiner and Gold. Excellent reference for a variety of FFT algorithms often with a good hardware perspective.

  • Digital Signal Processing: A System Design Approach, DeFatta, Lucas, and Hodgkiss. Contains good explanations and examples of multi-rate processing.

  • Other references

    • Computer Arithmetic, Algorithms and Hardware Designs, Behrooz Parhami. More thorough treatment of digital arithmetic. Notation is sometimes more complex than it needs to be, but the content is usually there.

    • VLSI Digital Signal Processing Systems: Design and Implementation, Keshab K. Parhi. Overviews many important topics in DSP processor design, but concepts are presented in a rigorous mathematical manner that is often hard to understand.

Course Readings

Homework / Projects

Future details are tentative.

Number	Due Date	Tentative % Hwk/proj grade	Material covered
1	Mon, Jan 24, 5:00 pm	20%	Binary arithmetic and conversion, verilog, and many-input adders
2	Fri, Feb 11, 5:00 pm	20%	Synthesis, adders, pipelining
3	Wed, Feb 23, 5:00 pm	20%	Digital filter tools, design, and optimization; saturation
4	Th, Mar 17, 5:00 pm	40%	FFT butterfly, convolutional neural net kernel

Late work policy

All work for a particular hwk/project must be submitted at one time.

If an assignment is reviewed in class, no credit is possible for late work. If an assignment was not reviewed in class, there will be a 1/3 reduction of remaining credit per day (i.e., 100% → 67% → 44% → 30% ...).

Normally late work can not be accepted after its deadline however if a serious issue such as an illness prevents you from completing work on time, obtain a verifiable written excuse, bring it to the instructor, and something will be worked out.

The EEC 281 Course Collaboration Policy

Grading errors

Please request grading corrections within a week of being returned to you. Non-obvious or very minor grading issues will not result in increased points—due to fairness to all students, the inherent subjectiveness of grading which is rife with both missing-points and additional-points imperfections, and because it is physically impossible to go through submitted work of every student in extreme detail (which would be required for near-perfect fairness).

To request a regrade, submit: 1) a short description of the suspected grading error, 2) the following statement on your regrade request with your signature immediately below it: "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct."

Course Topics, Slides, Notes, and Handouts

Date	Lecture	Handouts	Topics
Tue, January 4	1	Lecture 1 Course Introduction Key attributes of DSP processors Seven basic diagrams Chip design methodologies	Course introduction DSP overview Seven basic diagrams Chip design methodologies,
Th, January 6	2	Lecture 2 Quantization Noise and Word Size	Multiply-accumulate, FIR, convolution, dot products Quantization noise and word size
Tue, January 11	3	Lecture 3 Sign Extension Floating Point	Number representations: fixed-pt integer: unsigned, signed Sign extension for 2's complement Number representations: fixed-pt fractional Number representations: Floating point
Th, January 13	4	Lecture 4 Float-Fixed conversion	Number representations: Block floating point Number representations: Redundant (carry-save) 3:2 and 4:2 carry-save adders Fast carry-save addition Floating pt to fixed pt conversion
Tue, January 18	5	Lecture 5 Adders & subtractors Adders: Efficient Multiple Input Verilog 1: Overview	Adders & subtractors Adders: multiple-input Verilog Overview
Th, January 20	6	Lecture 6 Verilog 2: Language basics Verilog 3: Time and delay Verilog 4: Common mistakes Verilog 5: Testing Verilog 6: Decoder example Adders: Faster CPAs	Verilog Language basics Verilog Time and delay Verilog Common mistakes Verilog Hardware vs. testing Verilog decoder examples Adders: faster carry-propagate Carry-Select adders
Tue, January 25 Quiz 1 (zoom instructions)	7	Lecture 7	Carry-Lookahead adders
Th, January 27	8	Lecture 8 Flip-flops and registers Robust clock design Critical timing relationships, Rule #1 Synthesis	FFs, registers, and The 9 Rules Robust clock design Critical timing relationships, Review of rule #1 Synthesis
Tue, February 1	9	Lecture 9 Multipliers Booth encoding	Multipliers Booth encoding of multipliers Read Santoro paper (above)
Th, February 3	10	Lecture 10 Example Multiplier Squaring Fixed Input Multiplication dB	Example multiplier Squaring Fixed-input multiplication dB
Tue, February 8	11	Lecture 11 Digital Filter Coefficient Design	Digital filters Digital filter coefficient design Seeing the freq. response of filters
Th, February 10	12	Lecture 12 Estimating Spectral Magnitude FIR filter hardware Saturation	Estimating spectral magnitude of signals FIR filter hardware FIR scaling Saturation I
Tue, February 15 Quiz 2 (zoom instructions)	13	Lecture 13	Saturation II
Th, February 17	14	Lecture 14 Rounding	Saturation III Compression Rounding
Tue, February 22	15	Lecture 15 Drive Through Processing Complex Arithmetic	Drive through processing Complex addition, multiplication, rotation, format conversion
Th, February 24	16	Lecture 16 Complex Signal Magnitude Estimation Multiplier Scaling	Complex magnitude estimation Multiplication scaling
Tue, March 1	17	Lecture 17 Control and counters FSMs Gen Complex Functions Memories	Control circuits, state machine design Generating complex functions Memories: structure, types (6T SRAM, multi-port SRAM, ROM, DRAM) Memory uses in standard-cell ASIC designs
Th, March 3	18	Lecture 18 Signals in Time and Frequency DFT & FFT Background FFT Algorithms	Memories II Signals in time and frequency Discrete Fourier transform (DFT) fast Fourier transform (FFT) FFT processor architectures
Tue, March 8	19	Lecture 19 Multi-rate signal processing downsamp_movie.m Nyquist Filters Viterbi Decoding	Multi-rate processing Upsampling, decimation Nyquist filters Nyquist filters with upsampling Viterbi decoders
Th, March 10 Quiz 3 (zoom instructions)	20	Ref:Variable-freq clocking HW Ref:The RRI FFT Ref:Multiple Access Ref:DSSS Ref:DSSS Spreadsheet

Topical Outline

I.      Digital signal processing overview
        A.      DSP workloads
        B.      Example applications  
        C.      Programmable processors
II.     Processor building blocks
        A.      Verilog hardware description language
        B.      Binary number representations
        C.      Carry-propagate adders
        D.      Carry-save adders
        E.      Multipliers
        F.      Fixed-input multipliers
        G.      Complex arithmetic hardware
        H.      Memories
III.    DSP algorithms and systems
        A.      FIR filtering
        B.      Processor control and datapath integration
        C.      Multi-rate signal processing
        D.      Example systems: FFT, Viterbi, DSSS, CDMA,.
IV.     Design optimization
        A.      Verilog synthesis to a gate netlist
        B.      Delay estimation and reduction
        C.      Area estimation and reduction
        D.      Power estimation and reduction