EEC 281 - VLSI Digital Signal Processing
Winter 2017

Course Information

Course Readings

Read by Paper Comments
Th, Jan 12 Programmable DSP Architectures: Part I, Edward A. Lee, ASSP Magazine, October 1988. Easy to read article on the most notable features of programmable DSP processors. These first-generation DSP processors were more clearly distinguished from general-purpose processors than they are today. Note the publication date of 1988--many of the technical specifications are impressive only when considered in the context of the technology available at that time.
Reference Programmable DSP Architectures: Part II, Edward A. Lee, ASSP Magazine, January 1989. Easy to read article presenting an overview of issues of programming pipelined DSP processors with complex organizations.
Tue, Jan 17 Notes on ECE Machines and Tool Setup

Notes on ECE linux machines and your CAD tool environment setup
Tue, Jan 17 Notes on Running Verilog

Notes on running ncverilog here at UC Davis
Tue, Jan 17 Example code

Verilog code that may be helpful
Tue, Jan 17 Quick Reference For Verilog, Rajeev Madhavan [2up]

A very helpful and handy verilog reference
Tue, Jan 17
Verilog According To Tom, Tom Chanak Old but helpful intro to verilog. Please also read our accompanying notes. Skim.
Tue, Jan 17
An On-line Verilog Reference, S. Sutherland Convenient and very nicely presented. Note that it covers aspects of verilog that shouldn't be used for sythesizable code, such as signal strengths and primitives.
Reference A Signed Binary Multiplication Technique, A. D. Booth, Quarterly Journal of Mechanics and Applied Mathematics, June 1951. Classic paper introduces the Booth Algorithm.
Reference High-speed Arithmetic in Binary Computers, O. L. MacSorley, Proceedings of the IRE, January 1961. Classic paper introduces the Modified Booth's Algorithm which is commonly used in hardware implementations.
Tue, Jan 31 SPIM: A Pipelined 64 x 64-bit Iterative Multiplier, M. Santoro and M. Horowitz, IEEE Journal of Solid-State Circuits, April 1989. Classic paper is apparently the first to describe the 4:2 adder. It certainly contributed to the popular use of the 4:2 and its use in adding multiplier partial products.
Tue, Feb 7 Notes on Running Design Compiler

Notes and starter files for Synopsys' Design Compiler, and details on our standard cell library
Tue, Feb 14 Notes for running matlab
Simple matlab functions useful for 281FEB 23
Illustrative matlab examplesFEB 23
Notes for running matlab here at UC Davis, and some useful matlab functions and examples
Th, Feb 23
An Algorithm for the Machine Calculation of Complex Fourier Series, James W. Cooley and John W. Tukey, Mathematics of Computation, April 1965. The paper that popularized FFTs.
Th, Feb 23
Historical Notes on the Fast Fourier Transform, James W. Cooley, Peter A. W. Lewis, and Peter D. Welch; Proceedings of the IEEE, October 1967. Some notes on FFT history 2 years after the seminal paper.
Th, Mar 8 Trends in Multicore DSP Platforms, Karam, AlKamal, Gatherer, Frantz, Anderson, Evans, IEEE Signal Processing Magazine, November 2009. A paper with a thorough and detailed survey of modern multicore DSP processors
Reference A 28nm 0.6V Low-Power DSP for Mobile Applications, G. Gammie et al. A paper presented at ISSCC 2011.
Reference A 275mW Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer, H.-E. Kim et al. A paper presented at ISSCC 2011.

Homework / Projects

Course Topics, Slides, Notes, and Handouts

Future details are tentative and some slides will be updated during the quarter and marked .

Date Lecture Handouts Topics
Tue, January 10 1 Lecture 01
1:Fabrication Technologies
2:Quantization Noise
Course introduction, DSP overview, overview of "context" implementation technologies
Th, January 12 2 3:Sign Extension MAC; FIR, convolution, dot products
Number representations: integer
Tue, January 17 3 4:Floating Point Number representations: fractional, unsigned, signed; Sign extension; Floating point, Block floating point, Redundant number representations (carry-save), 3:2 and 4:2 carry-save adders,
Th, January 19 4 5:Verilog I Fast carry-save addition, Verilog I,

Tue, January 24 5 6:Verilog testing
7:Pipelined Block Diagrams
Hardware verilog vs. testing verilog,
Adders: carry-propagate vs. carry-save
Subtraction, ripple, carry-select adders
Carry-lookahead adders
Th, January 26 6 9:Efficient Multiple Input Addition
Multiple-input signed addition,
Booth encoding,
  Tue, January 31 7 Quiz 1 (25%)
11:Example Multiplier
13:Verilog II FEB 9, SLIDE 205
Multipliers II,
Verilog II,
Th, February 2 8 14:Verilog Control
15:Drive Through Processing
Drive through processing,
Control circuits, state machine design
Tue, February 7 (ISSCC) 9 16:Squaring
17:Fixed Input MultiplicationFEB 9, SLIDE 241
18:Multiplier Scaling
Quiz 1 review,
Fixed-input multiplies,
Multiplication scaling
Th, February 9 10 19:Complex ArithmeticFEB 9, SLIDES 262-263
Complex addition, mult, rotation, format conversion;
  Tue, February 14 11 Quiz 2 (35%)
20:Complex Signal Magnitude Estimation
21:SaturationFEB 23, SLIDES 277-284; FEB 28, SLIDES 279-280
22:RoundingFEB 16, SLIDES 296-299
Complex magnitude estimation,
Saturation and Compression,
Th, February 16 12 23:Fourier Pairs
Fourier Transform,
Tue, February 21 13 25:Filter Coefficient Design
26:Estimating Spectral Magnitude
27:FIR Scaling
Filter design
Th, February 23
14 28:DFT & FFT Background
29:FFT Algorithms
Discrete Fourier transform (DFT),
fast Fourier transform (FFT)
Tue, February 28
15 Quiz 3 (40%)
30:The RRI FFT
31:FFT Spiffee Example
32:FFT Chips
FFT processor architectures,
FFT processor example,
Memories: structure, types (6T SRAM, multi-port SRAM, ROM, DRAM), uses in standard-cell ASIC designs
Th, March 2
16 34:Multi-rate signal processing
Multi-rate processing,
Upsampling, decimation,
Tue, March 7 17 36:Clocks
37:Nyquist Filters
Clock design,
Nyquist filters,
Nyquist filters with upsampling,
Th, March 9
18 38:DC Offset
39:Automatic gain control
40:Multiple Access
42:DSSS Spreadsheet
DC offset,
Automatic gain control,
Multiple access,
Spread spectrum, CDMA, DSSS,
Tue, March 14
19 43:Viterbi Decoding

Viterbi decoders

Th, March 16

Convolution using DFT/FFTs
Wed, March 22
    Final Exam

Topical Outline

I.      Digital signal processing overview
        A.      DSP workloads
        B.      Example applications  
        C.      Programmable processors
II.     Processor building blocks
        A.      Verilog hardware description language
        B.      Binary number representations
        C.      Carry-propagate adders
        D.      Carry-save adders
        E.      Multipliers
        F.      Fixed-input multipliers
        G.      Complex arithmetic hardware
        H.      Memories
III.    DSP algorithms and systems
        A.      FIR filtering
        B.      Processor control and datapath integration
        C.      Multi-rate signal processing
        D.      Example systems: FFT, Viterbi, DSSS, CDMA,.
IV.     Design optimization
        A.      Verilog synthesis to a gate netlist
        B.      Delay estimation and reduction
        C.      Area estimation and reduction
        D.      Power estimation and reduction

Last update: April 06, 2017