Digital signal processors, building blocks, and algorithms. Design and implementation of processor algorithms, architectures, control, functional units, and circuit topologies for increased performance and reduced circuit size and power dissipation.
Goals: Through this course, students will develop the necessary skills to design simple synthesizable processors suitable for numerically intensive processing with an emphasis on small chip area and high-performance. Secondly, students will learn to design processors for simple digital signal processing tasks through the simultaneous design of DSP algorithms, processor architectures, and hardware design.
| Read by | Paper | Comments |
| Th, Jan 10 | Programmable DSP Architectures: Part I, Edward A. Lee | Easy to read article on the most notable features of programmable DSP processors. These first-generation DSP processors were more clearly distinguished from general-purpose processors than they are today. Note the publication date of 1988--many of the technical specifications are impressive only when considered in the context of the technology available at that time. |
| Tue, Jan 15 | Notes on ECE machines and linux | Notes on ECE linux machines and your linux environment setup here at UC Davis |
| Tue, Jan 15 | Notes on Running Verilog | Notes on running ncverilog here at UC Davis |
| Tue, Jan 15 | Example code | Verilog code that may be helpful |
| Tue, Jan 15 | Quick Reference For Verilog, Rajeev Madhavan [2up] | A very helpful and handy verilog reference |
| Tue, Jan 15Skim. | Verilog According To Tom, Tom Chanak | Old but helpful intro to verilog. Please also read our accompanying notes. Skim. |
| Tue, Jan 15Skim. | An On-line Verilog Reference, S. Sutherland | Convenient and very nicely presented. Note that it covers aspects of verilog that shouldn't be used for sythesizable code, such as signal strengths and primitives. |
| Tue, Jan 29 | SPIM: A Pipelined 64 x 64-bit Iterative Multiplier, M. Santoro and M. Horowitz | Classic paper introduces 4:2 adder and its use in adding multiplier partial products. An iterative architecture was chosen to reduce the amount of die area required. |
| Th, Feb 14 | Notes on Running Matlab | Notes on running matlab here at UC Davis, and some useful matlab functions |
| Th, Feb 14 | Notes on Running Design Compiler | Notes and starter files for Synopsys' Design Compiler, and details on our standard cell library |
| Th, Feb 21 Skim. |
An Algorithm for the Machine Calculation of Complex Fourier Series, James W. Cooley and John W. Tukey, Mathematics of Computation, April 1965. | The paper that popularized FFTs. |
| Th, Feb 21 Skim. |
Historical Notes on the Fast Fourier Transform, James W. Cooley, Peter A. W. Lewis, and Peter D. Welch; Proceedings of the IEEE, October 1967. | Some notes on FFT history 2 years after the seminal paper. |
| Th, Mar 6 | Trends in Multicore DSP Platforms, Karam, AlKamal, Gatherer, Frantz, Anderson, Evans | A recent paper with a thorough and detailed survey of modern multicore DSP processors |
| - | A 28nm 0.6V Low-Power DSP for Mobile Applications, G. Gammie et al. | A recent paper presented at ISSCC 2011. |
| - | A 275mW Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer, H.-E. Kim et al. | A recent paper presented at ISSCC 2011. |
| - | Programmable DSP Architectures: Part II, Edward A. Lee | Easy to read article presenting an overview of issues of programming pipelined DSP processors with complex organizations. |
| Number | Due Date | % Hwk/proj grade | Material covered |
| 1 | Fri, Jan. 25, 4:00pm | 15% | Binary arithmetic and conversion, verilog, and many-input adders |
| 2 | Th, Feb. 14, 9:00am | 20% | Synthesis and multipliers |
| 3 | Th, Mar. 7, 9:00 am | 30% | FIR filters |
| 4 | Fri, Mar. 22, 6:00pm | 35% | Complex exponential generator, CDMA transmitter |
| Date | Lecture | Handouts | Topics |
| Tue, January 8 | 1 |
Lecture 01
|
Course introduction, DSP overview |
| Th, January 10 | 2 |
News:graphics, video, and other media processing 1:QuantizationNoise 2:FabricationTechnologies
|
MAC; FIR, convolution, dot products; overview of "context" implementation technologies |
| Tue, January 15 | 3 | 3:SignExtension | Number representations: integer, fractional, unsigned, signed; sign extension |
| Th, January 17 | 4 | 4:FloatingPt | Floating point, block floating point, redundant number representations (carry-save) |
| Tue, January 22 | 5 |
5:Verilog I
|
3:2 and 4:2 carry-save adders, Verilog I, |
| Th, January 24 | 6 | 6:Verilog testing |
Hardware verilog vs. testing verilog,
Adders: carry-propagate vs. carry-save Subtraction, ripple, carry-select adders Carry-lookahead adders |
| Tue, January 29 | 7 |
7:EfficMultInputAddition
|
Multiple-input signed addition Multipliers |
| Th, January 31 | 8 |
Quiz 1 8:BoothEnc, 9:ExampMult | Multipliers II, Booth encoding; Verilog II, |
| Tue, February 5 | 9 |
10:Synthesis,
11:Verilog II,
12:VerilogControl,
13:DriveThroughProc,
|
Control circuits, state machine design, enableable registers Drive through processing, Squaring |
| Th, February 7 | 10 | 14:Squaring, 15:FixedInputMults, 16:MultScaling, 17:ComplexArith, | Fixed-input multiplies and scaling; complex arithmetic |
| Tue, February 12 | - | ISSCC, no lecture | |
| Th, February 14 | 12 |
Quiz 2 18:ComplexSigMagEst, 19:Saturation, 20:Rounding, 21:FourierPairs, |
Complex rotations, conversions, and amplitude estimation,
synthesis,
Saturation, rounding, Fourier Transform, |
| Tue, February 19 | 13 | 22:dB, 23:FiltCoeffDesign, 24:SignalMags, | Filters, filter design |
| Th, February 21 | 14 | 25:FilterResponse, 26:FIRScaling, | Filter design II |
| Tue, February 26 | 15 | 27:DFT&FFTbackground, 28:FFTDiagramsAlgs, | Discrete Fourier transform (DFT), fast Fourier transform (FFT) |
| Th, February 28 |
16 |
Quiz 3 29:FFT.RRI, |
FFT processors |
| Tue, March 5 |
17 | 30:FFTspiffee, 31:FFTchips, |
FFT processor example, |
| Th, March 7 8:15am-10:20am 70 Social Sci |
18 | 32:Memories, 33:Multi-rate, 34:Upsampling, 35:Decimation | Memories: structure, types (6T SRAM, multi-port SRAM, ROM, DRAM) Multi-rate processing, Upsampling, decimation, |
| Tue, March 12 8:15am-10:20am 70 Social Sci |
19 | downsamp_movie.m, 36:MultipleAccess, 37:CDMA, 38:DSSSspreadsheet, 39:NyquistFilters |
Multiple access,
Spread spectrum, CDMA, DSSS, Nyquist filters, Nyquist filters with upsampling, |
| Th, March 14 |
20 |
40:DCoffset,
41:Automatic gain control ,
42:Viterbi,
|
DC offset, Automatic gain control, Viterbi decoders Convolution using DFT/FFTs; Area, speed, power tradeoffs |
| Fri, March 22 6:00-8:00pm 123 Wellman |
- | Final Exam |
I. Digital signal processing overview
A. DSP workloads
B. Example applications
C. Programmable processors
II. Processor building blocks
A. Verilog hardware description language
B. Binary number representations
C. Carry-propagate adders
D. Carry-save adders
E. Multipliers
F. Fixed-input multipliers
G. Complex arithmetic hardware
H. Memories
III. DSP algorithms and systems
A. FIR filtering
B. Processor control and datapath integration
C. Multi-rate signal processing
D. Example systems: FFT, Viterbi, DSSS, CDMA,.
IV. Design optimization
A. Verilog synthesis to a gate netlist
B. Delay estimation and reduction
C. Area estimation and reduction
D. Power estimation and reduction
Submit to the instructor: 1) a short description of the suspected grading error, 2) the following statement on your regrade request with your signature immediately below it: "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct."