EEC 281 - VLSI Digital Signal Processing
Winter 2024

Course Information

• Instructor
  Bevan Baas

• Teaching Assistant
  Derek Li
  dsli@ucdavis.edu

• Office hours
  Tue 4:50 pm after lecture
  Wed 2:00 – 3:00pm, Kemper 2101
  Th 4:50 pm after lecture

• Lecture
  TTh 3:30–4:50 pm
  Olson 101

• Prerequisites: EEC 151 (formerly 150B), EEC 170, and EEC 180; or consent of instructor

• Catalog description

  Digital signal processors, building blocks, and algorithms. Design and implementation of processor algorithms, architectures, control, functional units, and circuit topologies for increased performance and reduced circuit size and power dissipation.

  Goals: Through this course, students will develop the necessary skills to design simple synthesizable processors suitable for numerically intensive processing with an emphasis on small chip area and high-performance. Secondly, students will learn to design processors for simple digital signal processing tasks through the simultaneous design of DSP algorithms, processor architectures, and hardware design.

• Grading

  • 60%   Homework/Projects (4)
  • 40%   Quizzes (2)

  Quizzes cover material through the end of the previous lecture with a general emphasis on more recent material. You may bring one page of double-sided hand-written (no photocopying) notes to the quizzes.

• Textbook: None required to purchase.

• Suggested references
  • Fundamentals of Digital Logic, with Verilog Design, Stephen Brown and Zvonko Vranesic. McGraw-Hill, 2003. Good overview of digital system design and many major building blocks with helpful verilog examples.

  • Computer Architecture, A Quantitative Approach, John Hennessy and David Patterson. Morgan Kaufmann, third edition, 2003. Probably the best reference for processor architectures. You should know this material already, so re-read material if you are rusty.

  • Getting Started with Matlab, Rudra Pratap. Oxford University Press, 2002. If you need a little help learning matlab, buy and read this. Chapter 2 has some nice tutorials, chapter 3 summarizes basic functions and file I/O, chapter 4 covers scripts, and chapter 6 gives a good overview of graphing. Concise with good coverage. $30 on amazon

  • Discrete-time Signal Processing, Oppenheim and Schaefer. Excellent reference for discrete-time systems, filtering, DFT, and other DSP algorithms.

  • Theory and Application of Digital Signal Processing, Rabiner and Gold. Excellent reference for a variety of FFT algorithms often with a good hardware perspective.

  • Digital Signal Processing: A System Design Approach, DeFatta, Lucas, and Hodgkiss. Contains good explanations and examples of multi-rate processing.

  • Other references

    • Computer Arithmetic, Algorithms and Hardware Designs, Behrooz Parhami. More thorough treatment of digital arithmetic. Notation is sometimes more complex than it needs to be, but the content is usually there.

    • VLSI Digital Signal Processing Systems: Design and Implementation, Keshab K. Parhi. Overviews many important topics in DSP processor design, but concepts are presented in a rigorous mathematical manner that is often hard to understand.

Course Readings

Homework / Projects

Future details are tentative.

Number	Due Date	Tentative % course grade	Material covered
1	Th, Jan 25, 3:30 pm	15%	Binary arithmetic and conversion, verilog, and many-input adders
2	Fri, Feb 9, 4:00 pm	10%	Synthesis, adders, pipelining
3	Mon, Feb 26, 4:00 pm	12%	Digital filter tools, design, and optimization; saturation; rounding
4	Wed, Mar 20, 11:59 pm	23%	Complex exponential generator, SAD processor

Late work policy

All work for a particular hwk/project must be submitted at one time.

If an assignment is reviewed in class, no credit is possible for late work. If an assignment was not reviewed in class, there will be a 1/3 reduction of remaining credit per day (i.e., 100% → 67% → 44% → 30% ...).

Normally late work can not be accepted after its deadline however if a serious issue such as an illness prevents you from completing work on time, obtain a verifiable written excuse, bring it to the instructor, and something will be worked out.

The EEC 281 Course Collaboration Policy

Grading errors

Please request grading corrections within a week of being returned to you. Non-obvious or very minor grading issues will not result in increased points—due to fairness to all students, the inherent subjectiveness of grading which is rife with both missing-points and additional-points imperfections, and because it is physically impossible to go through submitted work of every student in extreme detail (which would be required for near-perfect fairness).

To request a regrade, submit: 1) a short description of the suspected grading error, 2) the following statement on your regrade request with your signature immediately below it: "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct."

Course Topics, Slides, Notes, and Handouts

Date	Lecture	Handouts	Topics
Tue, January 9	1	Course Introduction Key attributes of DSP processors	Course introduction DSP overview Seven basic diagrams Chip design methodologies,
Th, January 11	2	Basic diagramsJAN 16 Chip design methodologies Quantization Noise and Word Size	the multiply-accumulator (MAC), convolution, FIR, dot products Quantization noise, word width, and SNR Number representations: fixed-pt integer: unsigned
Tue, January 16	3	Sign Extension Floating Point	Number representations: fixed-pt integer: signed Sign extension for 2's complement Number representations: fixed-pt fractional Number representations: Floating point Number representations: Block floating point Number representations: Redundant (carry-save) 3:2 carry-save adders
Th, January 18	4	Float-Fixed conversion Adders & subtractors Adders: Efficient Multiple Input	4:2 carry-save adders Fast carry-save addition Floating pt to fixed pt conversion Adders & subtractors Adders: multiple-input
Tue, January 23	5	Lecture 5 Verilog 1: Overview Verilog 2: Language basics Verilog 3: Time and delay Verilog 4: Common mistakes Verilog 5: Testing Verilog 6: Decoder example Adders: Faster CPAs	Verilog Overview Verilog Language basics Verilog Time and delay Verilog Common mistakes Verilog Hardware vs. testing Verilog decoder examples Adders: faster carry-propagate Carry-Select adders
Th, January 25	6	Lecture 6 Flip-flops and registers Robust clock design	Carry-Lookahead adders FFs, registers, and The 9 Rules Robust clock design
Tue, January 30	7	Critical timing relationships Synthesis Multipliers Booth encoding	Critical timing relationships Synthesis Multipliers Booth encoding of multipliers
Th, February 1	8	Example Multiplier Squaring Fixed Input Multiplication	Example multiplier Read paper by M. Santoro Squaring Fixed-input multiplication
Tue, February 6	9	dB Digital Filter Coefficient Design	dB Digital filters Time-domain convolution Frequency-domain multiplication Digital filter coefficient design Parks-McClellan and remez()
Th, February 8	10	Estimating Spectral Magnitude FIR filter hardware Saturation	Seeing the freq. response of filters Estimating spectral magnitude of signals FIR filter hardware FIR scaling Saturation I
Tue, February 13	11	Rounding	Saturation II Compression Rounding
Th, February 15	12	Drive Through Processing Complex Arithmetic	Drive through processing Complex addition, multiplication, rotation, format conversion
Tue, February 20 Quiz 1	13
Th, February 22	14	Complex Signal Magnitude Estimation Multiplier Scaling	Complex magnitude estimation Multiplication scaling
Tue, February 27	15	Control and counters FSMs	Control circuits Counters Finite state machine design
Th, February 29	16	Gen Complex Functions Memories	Generating complex functions Memories: categories, structures, types
Tue, March 5	17	Signals in Time and Frequency	Memories: macros, synthesized, off-chip Memories: using in standard-cell ASIC designs Signals in time and frequency
Th, March 7	18	DFT & FFT Background FFT Algorithms	Discrete Fourier transform (DFT) fast Fourier transform (FFT) FFT processor architectures
Tue, March 12	19	Lecture 19 Multi-rate signal processing downsamp_movie.m Nyquist Filters	Multi-rate processing Upsampling, decimation Nyquist filters Nyquist filters with upsampling Viterbi decoders
Th, March 14 Quiz 2	20	Ref: Viterbi Decoding Ref:Variable-freq clocking HW Ref:The RRI FFT Ref:Multiple Access Ref:DSSS Ref:DSSS Spreadsheet

Topical Outline

I.      Digital signal processing overview
        A.      DSP workloads
        B.      Example applications  
        C.      Programmable processors
II.     Processor building blocks
        A.      Verilog hardware description language
        B.      Binary number representations
        C.      Carry-propagate adders
        D.      Carry-save adders
        E.      Multipliers
        F.      Fixed-input multipliers
        G.      Complex arithmetic hardware
        H.      Memories
III.    DSP algorithms and systems
        A.      FIR filtering
        B.      Processor control and datapath integration
        C.      Multi-rate signal processing
        D.      Example systems: FFT, Viterbi, DSSS, CDMA,.
IV.     Design optimization
        A.      Verilog synthesis to a gate netlist
        B.      Delay estimation and reduction
        C.      Area estimation and reduction
        D.      Power estimation and reduction