Digital signal processors, building blocks, and algorithms. Design and implementation of processor algorithms, architectures, control, functional units, and circuit topologies for increased performance and reduced circuit size and power dissipation.
Goals: Through this course, students will develop the necessary skills to design simple synthesizable processors suitable for numerically intensive processing with an emphasis on small chip area and high-performance. Secondly, students will learn to design processors for simple digital signal processing tasks through the simultaneous design of DSP algorithms, processor architectures, and hardware design.
| Read by | Paper | Comments |
| Th, Jan 12 | Programmable DSP Architectures: Part I, Edward A. Lee | Easy to read article on the most notable features of programmable DSP processors. These first-generation DSP processors were more clearly distinguished from general-purpose processors than they are today. Note the publication date of 1988--many of the technical specifications are impressive only when considered in the context of the technology available at that time. |
| Tue, Jan 17 | Programmable DSP Architectures: Part II, Edward A. Lee | Easy to read article presenting an overview of issues of programming pipelined DSP processors with complex organizations. |
| Tue, Jan 17 | Notes on ECE machines | Notes on ECE linux machines here at UC Davis |
| Tue, Jan 17 | Notes on Running Verilog | Notes on running ncverilog here at UC Davis |
| Tue, Jan 17 | Example code | Verilog code that may be helpful |
| Tue, Jan 17 | Quick Reference For Verilog, Rajeev Madhavan [2up] | A very helpful and handy verilog reference |
| Tue, Jan 17Skim. | Verilog According To Tom, Tom Chanak | Old but helpful intro to verilog. Please also read our accompanying notes. Skim. |
| Tue, Jan 17Skim. | An On-line Verilog Reference, S. Sutherland | Convenient and very nicely presented. Note that it covers aspects of verilog that shouldn't be used for sythesizable code, such as signal strengths and primitives. |
| Tue, Jan 31 | SPIM: A Pipelined 64 x 64-bit Iterative Multiplier, M. Santoro and M. Horowitz | Classic paper introduces 4:2 adder and its use in adding multiplier partial products. An iterative architecture was chosen to reduce the amount of die area required. |
| Th, Feb 16 | Notes on Running Matlab | Notes on running matlab here at UC Davis, and some useful matlab functions |
| Th, Feb 16 | Notes on Running Design Compiler | Notes and starter files for Synopsys' Design Compiler, and details on our standard cell library |
| Th, Feb 23 Skim. |
An Algorithm for the Machine Calculation of Complex Fourier Series, James W. Cooley and John W. Tukey, Mathematics of Computation, April 1965. | The paper that popularized FFTs. |
| Th, Feb 23 Skim. |
Historical Notes on the Fast Fourier Transform, James W. Cooley, Peter A. W. Lewis, and Peter D. Welch; Proceedings of the IEEE, October 1967. | Some notes on FFT history 2 years after the seminal paper. |
| Th, Mar 8 | Trends in Multicore DSP Platforms, Karam, AlKamal, Gatherer, Frantz, Anderson, Evans | A recent paper with a thorough and detailed survey of modern multicore DSP processors |
| - | A 28nm 0.6V Low-Power DSP for Mobile Applications, G. Gammie et al. | A recent paper presented at ISSCC 2011. |
| - | A 275mW Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer, H.-E. Kim et al. | A recent paper presented at ISSCC 2011. |
| Number | Due Date | % Hwk/proj grade | Material covered |
| 1 | Fri, Feb. 3, 4:00pm | 20% | Binary arithmetic and conversion, verilog, and many-input adders |
| 2 | Fri, Feb. 24, 4:00pm | 20% | Synthesis and fixed-input multipliers |
| 3a | Th, Mar. 15, 12:00 noon | 30% | Problem 1 and 2abc |
| 3b | Tue, Mar. 20, 4:00pm | 30% | Problem 2defg |
| Date | Lecture | Handouts | Topics |
| Tue, January 10 | 1 |
Lecture 01 1:QuantizationNoise |
Course introduction, DSP overview |
| Th, January 12 | 2 | News:graphics, video, and other media processing 2:FabricationTechnologies | MAC; FIR, convolution, dot products; overview of "context" implementation technologies |
| Tue, January 17 | 3 | 3:SignExtension | Number representations: integer, fractional, unsigned, signed; sign extension |
| Th, January 19 | 4 | 4:FloatingPt | floating point, block floating point, redundant number representations |
| Tue, January 24 | 5 | 5:Verilog I | 3:2 and 4:2 carry-save adders, verilog I, |
| Th, January 26 | 6 |
6:Verilog testing
|
hardware verilog vs. testing verilog, Adders: carry-propagate vs. carry-save, subtraction, ripple, carry-select adders Carry-lookahead adders |
| Fri, January 27 10:00-11:20am Wellman 109 |
7 | 7:EfficMultInputAddition |
Quiz #1 Multiple-input sign extension, multipliers, |
| Tue, January 31 | 8 | 8:BoothEnc, 9:ExampMult, 10:Verilog II, | Multipliers II, Booth encoding; verilog II, |
| Th, February 2 | 9 |
11:VerilogControl,
12:DriveThroughProc ,
13:Squaring,
14:FixedInputMults,
15:MultScaling |
control circuits, state machine design, enableable registers Drive through processing, squaring, |
| Tue, February 14 | 10 |
16:ComplexArith
|
Fixed-input multiplies and scaling; complex arithmetic |
| Th, February 16 | 11 | 17:ComplexSigMagEst, 18:Saturation, 19:Rounding, 20:Synthesis, | Complex rotations, conversions, and amplitude estimation, synthesis, |
| Fri, February 17 9:00-10:20am Wellman 201 |
12 | 21:FourierPairs, | Saturation, rounding, Fourier Transform, |
| Tue, February 21 | 13 |
22:dB,
23:FiltCoeffDesign,
24:SignalMags,
|
filters, filter design |
| Th, February 23 | 14 | 25:FilterResponse, 26:FIRScaling, | Filter design II |
| Tue, February 28 | 15 |
27:DFT&FFTbackground
28:FFTDiagramsAlgs
|
Discrete Fourier transform (DFT), fast Fourier transform (FFT) |
| Th, March 1 |
16 | 29:FFT.RRI, |
Quiz #2 FFT processors |
| Tue, March 6 |
17 | 30:FFTspiffee, 31:FFTchips, 32:Memories (minor updates), | FFT processor example, Memories, |
| Th, March 8 |
18 | 33:Multi-rate, 34:Upsampling, 35:Decimation | Multi-rate processing, Upsampling, decimation, |
| Tue, March 13 |
19 |
downsamp_movie.m,
36:DCoffset,
37:NyquistFilters
|
Quiz #3 DC offset, Automatic gain control, Nyquist filters, Nyquist filters with upsampling, |
| Th, March 15 |
20 | 38:Viterbi 39:MultipleAccess 40:CDMA, 41:DSSSspreadsheet, | Convolution using DFT/FFTs, Viterbi decoders Multiple access, CDMA, DSSS, Area, speed, power tradeoffs |
| Th, March 22 3:30-5:30pm 144 Olson |
- | Final Exam |
Submit to the instructor: 1) a short description of the suspected grading error, 2) the following statement on your regrade request with your signature immediately below it: "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct."