• for loops

  1. Never use for loops in your hardware verilog—only in verilog used for test code.

  2. When using for loops, watch out if you use a register as a loop counter and you want the loop to count through all possible values. In the example below, the 4-bit number can never exceed 15 and the loop will run indefinitely.

     reg [3:0] in_a;
     for (in_a=0; in_a<=15; in_a=in_a+1) begin
        ...
     end 

  It's generally better to use an integer as a loop counter.

• mixing bitwise and logical operators

  Be careful to not mix bitwise operators (e.g., "|", "&", etc.) with logical operators (e.g., "||", "&&", etc.). Sometime they will produce the same result; sometimes not.

• "begin" and "end"

  If you don't use begin and end for "for" loops, "if" statements, and "case" blocks, verilog will execute only the next statement which may be very different from what you are expecting.

• $finish

  Using $finish is the best way to halt your simulation if you have free-running circuits (e.g., a clock generator). However, if you run vcs with virsim interactively, the crummy virsim interface wedges and you can't get virsim to run the simulation.

• signed numbers

  Signed multiplies are done only when both inputs are declared signed. For example,

     reg signed [7:0] input1, input2;
     

  $write() prints negative numbers only when variable is signed.

• assigning one reg in more than one always block

  Don't set the same register in more than one always block--the resulting operation can be ambiguous and if you synthesize the code, the tool will give you an error.

• Use $write() statements

  Use lots of $write, $display, or $monitor statements to print out wires, registers, and other variables.

• Start from the inputs and work towards the outputs

  Verify the inputs are as you expect and then work a stage/level at a time until you get to the outputs. When you find an error, focus 100% on fixing the first one you find before moving on.

Written by Bevan Baas

2018/02/16  Minor changes. Emphasize no for loops in hardware verilog.
2025/01/13  Minor edits.