EEC 281 Design Compiler Notes

ECE machines which run Design Compiler

A few Design Compiler Clarifications, Pitfalls, and Suggestions

Design Compiler Files and Example Design

Configuration changes you must make

Finding the maximum possible clock frequency (minimum cycle time)

  1. Set the clock period to a very short cycle time such as 0.1 ns (10 GHz)

  2. Synthesize the design

  3. Unless the circuit is extremely simple, there will be a negative slack result. Use the equation in the handout to calculate the minimum achievable clock cycle time.

Finding the minimum possible circuit area

  1. Set the clock period to a very long cycle time such as 1000 ns (1 MHz)

  2. Synthesize the design

  3. Unless the circuit has an extremely long logic depth between pipeline registers, there will be a positive slack result. The area result is the minimum achievable circuit area.

The Standard Cell Library We Use

Running a Simulation Using Your Synthesized Gates (NO LONGER SUPPORTED)

Digging deeper into DC

Odd Things That Should Be Fixed

EEC 281 | B. Baas | ECE Dept. | UC Davis
Written by Bevan Baas with valuable help from Gabriel Ricardo, Bart Zeydel, Eric Work, Zhibin Xiao, Jon Pimentel, and Shifu Wu.
2021/02/08  Added or2.v example, updated Makefile and dc-template.tcl
2020/03/03  Added fsm.v and fsm.vfs
2020/02/07  Added sections to find max clock frequency and minimum area
2017/02/04  Major changes for new NanGate 45 nm library
2015/02/03  Added SEQGEN note
2015/01/16  Minor changes
2010/02/17  A few small changes
2010/02/16  Updated path to vtvtlib25.v
2009/02/13  Some updates