Verilog modules which may be helpful:

• prob1.v

• prob1_ref.v

• prob1.vt

• cdma.vt — This module contains example code that writes output to a file using $fopen and $fwrite.

• threetwos_32.v — This module connects 32 3:2 adders connected in a carry-save arrangement. (unverified, but looks correct)

• fourtwos_32.v — This module connects 32 4:2 adders. Use it for this purpose or as a starting point to generate rows of 4:2 adders of other widths. (unverified, but looks correct)

Updates

2019/03/04  Added prob1* test modules
2018/02/16  Minor cleanup and moved modules to tutorial directories
2015/01/09  Minor cleanup
2006/02/28  First pass