Submit: (1) all *.v hardware and necessary testing code you wrote (no generated or provided files), and (2) other requested items such as diagrams.
Upload a pdf copy of (1) and (2) to Canvas (under "Assignments"). Add titles to pages and file names so it is clear to which problem they belong. For example, Problem 1, prob1.v, prob1.vt,... Place all of your answers and code into a single pdf file with all problems and material in order.
Diagrams. If a problem requires a diagram, include details such as datapath, memory, control, I/O, pipeline stages, word widths in bits, etc. There must be enough detail so that the exact functional operation of the block can be determined by someone with a reasonable knowledge of what simple blocks do. A satisfactory diagram may require multiple pages of paper taped together into a single large sheet.
Verilog. If a problem requires a verilog design, turn in paper copies of both hardware and test verilog code.
a table printed by your verilog testbench module listing all inputs and corresponding outputs,
a simvision waveform plot which shows (labeled and highlighted) corresponding inputs and outputs, or
test code which compares a) your hardware circuit and
b) a simple
reference circuit (using high-level functions such as "+")—no
Include two copy & paste sections of text from your
simulation's output (one for pass, and one for fail where you
purposely make a very small change to either your
designed hardware circuit or your reference circuit
to force the comparison to fail) that look something like this:
input=0101, out_hw=11110000, out_ref=11110000, ok
input=0101, out_hw=11110000, out_ref=11110001, Error!
For 1 and 3, the output must be copied & pasted directly from the simulator's output without any modifications.
In all cases, Show how you verified the correctness of your simulation's outputs.
Synthesis. If a problem requires synthesis, turn in paper copies of the following. Print in a way that results are easy to understand but conserves paper (multiple files per page, 8 or 9 point font, multiple columns). Delete sections of many repeated lines with a few copies of the line plus the comment: <many lines removed> .
The "always @(*)" verilog construct may be used but keep an eye out for any situations where Design Compiler may not be compatible with it.
Run all compiles with "medium" effort. Do not modify the synthesis script except for functional purposes (e.g., to specify source file names).
Functionality. For each design problem, you must write by hand 1) whether the design is fully functional, and 2) the failing sections if any exist.
Point deductions/additions. TotalProbPts is the sum of all points possible.
inA inB outExp outMantissa I Certify Correct -------- -------- ------ -------------- ----------------- 10101100 00110101 110010 01100110100101 Y 00000101 10110101 101010 01010101010101 Y 01010100 11101010 010100 11010101100101 no // this indicates I recognize there is an error here
Clarity. For full credit, your submission must be easily readable, understandable, and well commented.
For this homework/project, you may use the "always @(*)" verilog construct but keep an eye out for any situations where Design Compiler is not compatible with it.
[25 pts] The purpose of this problem is to familiarize you with the synthesis process and to give you a rough feeling for the size of a few simple circuits in our standard cell library's technology. Copy the files from the DC tutorial (see link on the main EEC281 page) to get started. Synthesize the following blocks and report their total cell area. Do not include registers (flip-flops) in these blocks. Also, do not declare any wires or registers as "signed", but assume words are all 2's complement signed unless stated otherwise. No need to simulate, but your verilog must compile correctly (run "make check"). Also, for this problem, do not worry if designs do not meet timing (negative slack time).
Turn in: 1) source verilog, 2) totals in a single table so it can be used as a note sheet in the future. Do not submit any output synthesis reports.
b) [2 pts] 3:2 adder using verilog "&" "|",
Draw your circuit and the circuit output by DC.
c) [2 pts] 3:2 adder using verilog "+".
d) [3 pts] 10-bit adder (11-bit output). Use "+" in verilog.
e) [5 pts] an adder which adds 17 6-bit numbers using verilog "+" (i.e., something like, assign out = in0 + in1 + in2 + ...) and produces a 6-bit sum.
f) [5 pts] your 17-input adder from hwk/proj 1, Problem 7. If your adder is not functional, improve it so it is at least synthesizable, synthesize it anyway, and write a note on your submission that it is not functional.
g) [3 pts] 8-bit x 8-bit unsigned multiplier (16-bit output). Use "*" in verilog.
h) [3 pts] 16-bit x 16-bit unsigned multiplier (32-bit output). Use "*" in verilog.
[20 pts] Build a ripple-carry adder with 16-bit inputs and 16-bit output using full adders from part 1(c). Register all inputs and outputs (to make synthesis timing accurate).
a) [10 pts] Write design in verilog, test with at least 15 test cases with a unique set of inputs calculated each clock cycle. Verify using method ***(3).
b) [10 pts] Synthesize the design with a high clock frequency to find the maximum clock rate. State the maximum clock rate and corresponding area. Submit *.area and *.tim (longest path only) reports only.
[25+10 pts] Repeat Problem 2 with a carry-select adder composed of two 8-bit sections.
[25+10+10 pts] Repeat Problem 2 with a carry-select adder composed of three sections whose widths are chosen to minimize delay.
c) [10 pts] Justify the partitioning you chose.
[25+10 pts] Repeat Problem 2 but pipeline the ripple-carry adder into 8 pipeline stages.
[5 pts] Write a single table with 1) max clock frequency and 2) area for problems 2–5.