EEC 281 - Homework/Project #2

Work individually, but I strongly recommend working with someone in the class nearby so you can help each other when you get stuck, with consideration of the Course Collaboration Policy. Please send an email to me if something is not clear and I will update the assignment using green font.

Notes:


Total: 165 points

For this homework/project, you may use the   "always @(*)"   verilog construct but keep an eye out for any situations where Design Compiler is not compatible with it.

  1. [25 pts] The purpose of this problem is to familiarize you with the synthesis process and to give you a rough feeling for the size of a few simple circuits in our standard cell library's technology. Copy the files from the DC tutorial (see link on the main EEC281 page) to get started. Synthesize the following blocks and report their total cell area. Do not include registers (flip-flops) in these blocks. Also, do not declare any wires or registers as "signed", but assume words are all 2's complement signed unless stated otherwise. No need to simulate, but your verilog must compile correctly (run "make check"). Also, for this problem, do not worry if designs do not meet timing (negative slack time).

    Turn in: 1) source verilog, 2) totals in a single table so it can be used as a note sheet in the future. Do not submit any output synthesis reports.

    Blocks

    a) [2 pts] bitwise AND of two 10-bit numbers (10-bit output)

    b) [2 pts] 3:2 adder using verilog "&" "|", "^", "~".
    Draw your circuit and the circuit output by DC.

    c) [2 pts] 3:2 adder using verilog "+".

    d) [3 pts] 10-bit adder (11-bit output). Use "+" in verilog.

    e) [5 pts] an adder which adds 17 6-bit numbers using verilog "+" (i.e., something like, assign out = in0 + in1 + in2 + ...) and produces a 6-bit sum.

    f) [5 pts] your 17-input adder from hwk/proj 1, Problem 7. If your adder is not functional, improve it so it is at least synthesizable, synthesize it anyway, and write a note on your submission that it is not functional.

    g) [3 pts] 8-bit x 8-bit unsigned multiplier (16-bit output). Use "*" in verilog.

    h) [3 pts] 16-bit x 16-bit unsigned multiplier (32-bit output). Use "*" in verilog.


  2. [20 pts] Build a ripple-carry adder with 16-bit inputs and 16-bit output using full adders from part 1(c). Register all inputs and outputs (to make synthesis timing accurate).

    a) [10 pts] Write design in verilog, test with at least 15 test cases with a unique set of inputs calculated each clock cycle. Verify using method ***(3).

    b) [10 pts] Synthesize the design with a high clock frequency to find the maximum clock rate. State the maximum clock rate and corresponding area. Submit *.area and *.tim (longest path only) reports only.


  3. [25+10 pts] Repeat Problem 2 with a carry-select adder composed of two 8-bit sections.


  4. [25+10+10 pts] Repeat Problem 2 with a carry-select adder composed of three sections whose widths are chosen to minimize delay.

    c) [10 pts] Justify the partitioning you chose.


  5. [25+10 pts] Repeat Problem 2 but pipeline the ripple-carry adder into 8 pipeline stages.


  6. [5 pts] Write a single table with 1) max clock frequency and 2) area for problems 2–5.



Updates:
2022/01/31  Posted