Currently, we are using only the Cadence NCVerilog simulator. Because complex issues may arise with the simulator and synthesis tools, I strongly recommend using Cadence rather than another verilog simulator.

If you experience problems starting the tools in our environment, email the course TA or me (Bevan Baas) or ece support.

Quick start tutorial files

Run ncverilog on tutorial files and start simulator

This approach runs the simulator separately from the waveform viewer.

Source verilog file(s)

Somewhere in your source verilog, add the following statements where they will be executed only once (likely in an initial begin block, and definitely in a test-bench module, not a "hardware" module).

$recordfile("DumpFileName");
$recordvars(TopLevelModuleName);

Your simulation signal traces will be stored in DumpFileName.dsn and DumpFileName.trn

Running the simulator
Run verilog with something like this command:

make run

You can add more source files into the *.vf file. Your output should look like the following. The first line is the command run by Makefile.

  
cobra_61> make run
ncverilog +access+r -l tbench.log -f tbench.vf
ncverilog(64): 15.20-s031: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
file: tbench.vt
        module worklib.tbench:vt
                errors: 0, warnings: 0
                Caching library 'worklib' ....... Done
        Elaborating the design hierarchy:
        Building instance overlay tables: .................... Done
        Generating native compiled code:
                worklib.tbench:vt <0x171601b8>
                        streams:  32, words: 38678
        Building instance specific data structures.
        Loading native compiled code:     .................... Done
        Design hierarchy summary:
                                  Instances  Unique
                Modules:                  1       1
                Registers:               22      22
                Scalar wires:             3       -
                Vectored wires:          13       -
                Always blocks:            5       5
                Initial blocks:           1       1
                Cont. assignments:       11      16
                Simulation timescale:  10ps
        Writing initial simulation snapshot: worklib.tbench:vt
Loading snapshot worklib.tbench:vt .................... Done
ncsim> source /apps/Cadence/INCISIVE152/tools/inca/files/ncsimrc
ncsim> run
Initialzing to 0
Simulation complete via $finish(1) at time 1300 NS + 0
./tbench.vt:180    $finish;             // ends simulation
ncsim> exit
cobra_62>

Starting the waveform viewer
To start the viewer, type:

make viewer

then select "File" → "Open Database..." → choose your *.trn file → click "Open & Dismiss". Your design should now show up in the "Scope Tree" section of the window. Select signals you would like to view by left clicking and then right click and select "Send to waveform viewer" to view signals in a new Waveform window.



Re-running a simulation
Simply re-run the simulation using "make run". After the simulation has completed, select File -> "Reload database..." in the waveform window and that's it!

More Documentation

For more advanced verilog information, two class handouts will be provided. For more detailed ncverilog information, type the following line:

64-bit systems:
acroread /net/pizza/tools/cadence/IUS81/doc/ncvlog/ncvlog.pdf &
32-bit systems:
acroread /net/pizza/tools/cadence/IUS62/doc/ncvlog/ncvlog.pdf &

A shorter description of various ncverilog command line options can be found by typing

ncverilog -h | less -Mq

Using viewer configuration files

Saving a viewer configuration file by selecting "File -> Save Command Script" after you have setup a waveform window with signals. Later (after quitting and restarting typically), select "File -> Source Command Script" to restore your waveform viewer to its previous state.

Updates

2018/02/16, 16:30  Minor updates, moved link to Pitfall page to top level page
2017/01/24, 16:00  Updates to page intro
2007/01/31, 23:45  Updated paths from /net/pizza/3/... to /net/pizza/8/...
2005/01/25, 12:45  Added "ssh" login info
2005/01/24, 15:45  Added "setenv CDS_*" to environment additions list
2005/01/21, 11:10  Filled out list of linux ECE machines
2005/01/20, 20:30  A number of updates including abc.v and tbench.sv
2005/01/20, 14:00  First pass

• Verilog tutorial by Deepak Tala.

Updates

2005/02/03         First pass

• Icarus verilog home page
• GTKWave home page

Binaries exist for most platforms, including windows. If you use cygwin for win32 to emulate the unix platform, you use "make" just like from a Linux machine. These programs will build without any problems on most unix based systems. This has worked well for me as well as been used for some commercial CPUs (from some sites I've read). I feel its a good fit for students or other users who don't need quite a complex system.

Installation instructions

Installing Icarus Verilog and GTKWave for MacOS X

Below is a list of required software and notes about the build process for the listed applications.

1. Apple's XCode: This can be found on the OS X install CD/DVD or downloaded through the Apple Developer Connection (http://developer.apple.com/). This will provide you with the gcc 3.3 compiler needed to compile the applications from the source code. The X11 SDK must also be installed which is an optional component during install.

2. Apple's X11: This provides an X11 interface for the GTKWave application which can be found on the install CD/DVD or downloaded (http://www.apple.com/macosx/features/x11/).

3. Fink: This provides a bridge between the Unix world and OS X and can be downloaded at http://fink.sourceforge.net/ (10.3 required). Look at the documentation on the website for installing FinkCommander and switching to the unstable tree. In the unstable tree you will find the "iverilog" and "gtkwave" packages. Due to dependencies it might take several hours to build all the required packages.

4. Download the Makefile.icarus from the website, name it "Makefile" and place it in a directory with the sample test bench code. With luck "make compile", "make run", and "make viewer" will work. Remeber to start X11 before running make viewer.

Below is a list of required software and setup process for using these tools with windows.

1. Cygwin: An enviornment, complete with the "make" utility, is required to use and build GTKWave. To do this obtain setup.exe from http://www.cygwin.com/. In addition to the default packages install: Devel => gcc, gtk+-devel, libxml2-devel ; X11 -> xorg-x11-base, xwinwm.

2. Go to the Icarus Verilog website and download the Windows setup package from the FTP. Install the program into C:\IVerilog or some other path without spaces. Add this location to your system PATH variable using the Windows "System" control panel applet.

3. Download the GTKWave source code from the GTKWave website and move the file into C:\cygwin\home\(USERNAME) and extract the archive.

4. Start a cygwin shell instance which should put you in your home directory. Build the application with "./configure --enable-builtin-readers="vcd"", then make, then make install. If you wish to use LXT files or other input formats you might need to apply the patch below using "patch -p1 < (PATCH_FILE)" in the extracted directory.

5. Download the Makefile.icarus from the website, name it "Makefile" and place it in a directory within your home folder with the sample test bench code. With luck "make compile", "make run", and "make viewer" will work. Before using make viewer, you must first run "/usr/X11R6/bin/startxwin.sh" to start and X11 session.

Here is a patch gtkwave.patch written by Eric to correct compile errors in cygwin.

Updates

2005/02/11         Installation process added (from Eric Work)
2005/02/02         First pass

ECE machines which run VCS

• perch.ece.ucdavis.edu
• pike.ece.ucdavis.edu
• sole.ece.ucdavis.edu
• sturgeon.ece.ucdavis.edu
• trout.ece.ucdavis.edu

Quick Start Tutorial Files

Update your .software file in home directory

To run VCS and Virsim for linux in the ECE department environment, the following two lines MUST be added to the .software file in your home directory (~/.software):

synopsys2002  #synopsys
VCS_7  #VCS

After adding the lines, you must log out and log back in for the changes to take effect.

Run VCS on tutorial files and start simulator

This approach runs the simulator separately from the waveform viewer and therefore does not use the integrated vcs environment described below. Some people find this easier to use because the "Simulator Control" step is eliminated.

Source verilog file(s)

Somewhere in your source verilog, add the following statements where they will be executed only once (likely in an initial begin block).

$vcdplusfile("prob1.vpd");     // .vpd extension is nice reminder
$vcdpluson;

Running the simulator
Run VCS with something like this command:

vcs -Mdir=/tmp/MyInitialsverilog -Mupdate -PP -R file1.v file2.v
   or simply
make run

Where file1.v and file2.v are source verilog files. Of course, you can add more source files and even include all source files in a separate file and include them with the -f command line option.

The -Mdir=/tmp/MyInitialsverilog option directs vcs to use your workstation's local /tmp disk for temporary compile files (can speed up your simulation significantly). Choose a unique name for your /tmp directory so there aren't conflicts with other students' directories.

The -PP option enables vcs to work with vcd+ files.

The -R option tells vcs to run the simulation after compilation.

Starting the waveform viewer
To start the viewer, don't run it directly by typing virsim as this (arrgh) brings up an old broken version. Instead, type

vcs -RPP &

then select File -> Open in the "VirSim - Hierarchy" window and choose your .vpd file. If you had previously saved a configuration file, open it from the File menu. If not, select Window -> Waveform and select signals from the "VirSim - Hierarchy" window and drag and drop them using your center mouse button into the "VirSim - Waveform" window.

The -RPP option puts vcs into post-processing mode so that vcs starts virsim for looking at a vcd+ file.

Re-running a simulation
Simply re-run the simulation using the above procedure (easiest to use a make target in a Makefile). After the simulation has completed, select File -> Reopen in the waveform window and that's it!

More Documentation

For more advanced verilog information, two class handouts will be provided. For a more detailed VCS/virsim tutorial, enter the following lines at a Linux terminal: (Note: your .software file must be updated for this to work, see section titled Update .software file in home directory above.

cd $VCS_HOME/examples/XVCSDEMO
acroread tutorial.pdf &

cd $VCS_HOME/doc/UserGuide/
acroread vcs.pdf &
acroread vsim.pdf &

A shorter description of various vcs command line options can be found by typing

vcs -help | less -Mq

Using Configuration Files

Saving a configuration file and Loading it (both from the File menu) is a convenient way to retain signals you have selected in the waveform viewer.

Another Way to Run VCS

Type the following command line in the directory where the previously-mentioned files are located:

make run_interactive

The -RI option starts-up Virsim immediately after vcs compiles the source files.
The -Mupdate option enables incremental compilation. This speeds up compiles when not all source files are modified, but most importantly, enables the GUI to work.
The "-l logfile" option specifies a log file where compilation and runtime messages are saved.

Once the simulator is invoked, open up the hierarchy window by selecting Window->Hierarchy in the Interactive window

1. Select TB from the left pane in the Hierarchy window (Several signals should appear in right pane)
2. Open the waveform window by selecting Window->Waveform in the interactive window
3. Use the left mouse button and shift key to select the all the Signals in the right pane of the hierarchy window
4. Use the left and right mouse buttons simultaneously to drag the selected signals into the waveform window
At the bottom of the interactive window next to the "Simulator Control" label, there is a drop down menu with 3 options:
1. "Step time" - will step the simulator for specified number of simulator increments (In DFF example the `timescale command set the simulator increment to 10ps. The increment is shown in parenthesis at the bottom left of the interactive window next to the "Time" label)
2. "Go to Time" - will run up to the specified time (again units here are in 10 ps for this example)
3. "Step Signal" - will run simulation until a change occurs on the specified signal
Once the simulator option has been chosen (choose step time 5000 for DFF example), hit "OK" and the simulator will execute and update all signals in the waveform window.

The waveform view can be changed by selecting Zoom in the waveform window.

Because of the delays specified in the initial block of TB.v, this simulation will need to be run to 675ns to complete. Do this by choosing "Go To Time" and entering 67500. Hit "OK" and adjust the zoom and the entire test simulation can be seen. Note: The simulator can be stopped using the red "Stop Simulation" button in the Interactive window

To re-run a simulation after making a change to a verilog source file, select Sim -> Rebuild and Re-exec and then follow the "Simulator Control" procedure above. Note that the -Mupdate option must be given for this to work.

2020/02/06  Minor edits (BB)
2020/01/27  Minor edits (BB)
2019/03/12  Minor edits (BB)
This document was written by Bevan Baas and Ryan Apperson with valuable help from Victor Yip.