EEC 281 - Homework/Project #4

Work individually, but I strongly recommend working with someone in the class nearby so you can help each other when you get stuck, with consideration of the Course Collaboration Policy. Please send an email to me if something is not clear and I will update the assignment using green font.

Notes:


Total: 400 points

1. [150 pts] Design a block which calculates the Y output of the complex radix-2 DIT FFT butterfly.

  Y = A - BW

The latency may be as many cycles as needed however the multipliers must be the only logic inside their own pipeline stages.

The block's I/O signals are described below. Recall that since there is no decimal point in the hardware, you may think of the inputs as being in any x.x format you like. Having done that, the decimal point of the output will be fixed and you will need to take that into consideration when comparing in matlab. Design and write verilog for the block. The test procedure is as follows:
  1. Generate test cases in your verilog testbench:
    1) A minimum of 20 hand-picked extreme case inputs (e.g., max pos and max neg inputs)
    2) A minimum of 1000 random inputs using $random (which returns a 32-bit number each time it is called). Use $random(seed) once at the beginning of your test to set the random number generator's seed to some arbitrary value so tests can be repeated for debugging.
    3) W inputs consist of random cases drawn from the first 6 multiples of –45°, i.e., –0°, –45°, –90°, –135°, –180°, –225° and you may include other valid WN values. Or in matlab, simply exp(-i*2*pi/8 * k) where k varies from zero to 5.

  2. Output both the a) inputs and b) verilog output to a plain-text matlab-readable *.m file. For example, a file such as:
    a_r(1) = -643; a_i(1) = 0; ... % matlab can not have index = 0
    a_r(2) = 123; a_i(2) = -6; ...
    a_r(3) = 000; a_i(3) = -243; ...
    where values can be printed out and then re-scaled in matlab however it is most convenient.

    Use "signed" reg's only for the printf statement. Suggestion: print integers in verilog.

  3. Compare a) verilog output and b) matlab calculation of the butterfly equations using difff.m in matlab. Do not scale the matlab equations from how they are written above, but you may scale your verilog output by any power-of-2—which is the same as selecting the location of the decimal point.

Synthesize your design at the following 3 cycle time values and report the 1) achieved cycle time (clock frequency) and 2) area for each:
  1. a very long cycle time, e.g., 1 ms = 1 KHz, to find the minimum area;

  2. a very short cycle time, e.g., 0.1 ns = 10 GHz, to find the minimum cycle time;

  3. the cycle time achieved in the synthesis run for case (2) multiplied times 1.5

Submit the following.



2. [250 pts] The Alexnet convolutional neural net is widely credited with the dramatic rise in popularity of neural nets. Read the 2012 Alexnet paper paying particular attention to Sections 1, 2, and 3.5. This project consists of building and synthesizing custom hardware for the first convolutional layer of Alexnet using a reduced image size. The primary specifications for this simplified project are as follows:

The testing environment is built as follows:

Other requirements:

Submit the following.

No points are possible for (c), (d), or (e) unless the design is fully functional and without synthesis errors or serious warnings.


Hint: See the Synthesis handout for details on the achievable cycle time and reading synthesis timing reports.

Hint: See the "matlab: tips for 281" web page for suggestions on addressing memories in matlab.



Updates:
2022/02/27  Posted
2022/03/14  Clarification regarding W inputs during testing