From 1987-89, he served as a new product engineer working on the processor for a high-end minicomputer in Hewlett Packard's Computer Systems Division, Cupertino, CA. In early 1999, he joined Atheros Communications [wikipedia] as the second full-time employee after the founders and served as a core member of the team which developed the first IEEE 802.11a (54 Mbps, 5 GHz) Wi-Fi wireless LAN solution. The chipset has been shipping in volume since September of 2001 and for one and a half years was the only shipping 802.11a chipset [ISSCC 2002]. Atheros became a publicly-held company in Feb. of 2004 and was purchased by Qualcomm in 2011.
In 2003, Dr. Baas joined the Department of Electrical and Computer Engineering at the University of California, Davis as an Assistant Professor, where he currently supervises research for more than ten graduate students. He became an Associate Professor in 2008, and a full Professor in 2015.
Dr. Baas' research interests are in the algorithms, applications, architectures, arithmetic, circuits, VLSI design, and software tools for high-performance, energy-efficient, and area-efficient computation with consideration of the challenges and opportunities of future fabrication technologies. He is interested in both programmable and special-purpose processors with an emphasis on DSP, multimedia, and embedded workloads with recent projects targeting datacenter and scientific workloads. Projects include the AsAP (Asynchronous Array of simple Processors) programmable array processor chip, applications, and tools [ISSCC 2006]; Low Density Parity Check (LDPC) decoders; FFT processors; viterbi decoders; and H.264 video codecs. The 0.18 μm AsAP 1 chip contains 36 programmable processors, operates at over 610 MHz at 2.0 V, and is believed to be the second highest clock rate processor designed in any university. His research group completed the design and fabrication of a second generation processing platform with 167 1.2 GHz processors in 65 nm CMOS [VLSI Symp 2008] which is believed to be the highest clock rate processor designed in any university. The chip contains 164 programmable processors that can each independently control their supply voltage and clock frequency; three highly-configurable special-purpose processors: Fast Fourier transform (FFT), H.264 video motion estimation, and Viterbi decoder; and three 1.3 GHz 16 KB shared memories.
Dr. Baas was a National Science Foundation Fellow from 1990-93 and a NASA Graduate Student Researcher Fellow from 1993-96. He received the National Science Foundation CAREER award in 2006, Best Paper Award at the IEEE International Conference on Computer Design 2011, Best Student Paper Award third place at IEEE International Midwest Symposium on Circuis and Systems 2015, Best Student Paper Award third place at IEEE Asilomar 2014, "WACIest" Best-In-Session Paper at ACM/IEEE Design Automation Conference (DAC) 2010, Best Paper nominations at IEEE Asilomar 2011 and IEEE BioCAS 2010. He supervised the research that earned the College of Engineering Zuhair A. Munir Award for Best Doctoral Dissertation Honorable Mention in 2013, and was awarded the Most Promising Engineer/Scientist Award by AISES in 2006. From 2007-12 he was an Associate Editor for the IEEE Journal of Solid-State Circuits and he has served as Guest Editor of IEEE Micro Special Issue, March 2012; and IEEE Design & Test of Computers Special Issue, January 2013. He has been a Visiting Professor at Intel's Circuit Research Lab in 2006, the University of Sydney in 2015-16, and the National University of Singapore in 2016. He has served and is serving as: Program Committee Co-Chair of the IEEE HotChips Symposium on High-Performance Chips 2011 and Program Committee member 2009, 2010; Parallel Architecture Co-Chair of the Design Automation Conference (DAC) 2011 Workshop on Parallel Algorithms, Programming, and Architectures; Technical Program Committee member of the International Conference on Computer Design (ICCD) 2004, 2005, 2007, 2008, 2009; Technical Program Committee member of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) 2010; Committee member of the International Solid-State Circuits Conference (ISSCC) Student Research Preview 2012, 2013, 2014; Technical Program Committee member of the IEEE/IFIP International Conference on Very Large Scale Integration (VLSI-SoC) 2014; Program Committee member of the IEEE/ACM International Workshop on Network on Chip Architectures (NoCArc) 2016; a member of the AISES Academic Advisory Council, and the Technical Advisory Board of an early stage technology company. He is a member of Tau Beta Pi, Phi Kappa Phi, Eta Kappa Nu, AISES, and a Senior Member of the IEEE.
A short bio, and a slightly longer bio which is not kept up to date.
My university web page
Dissertation, February 1999
"An Approach to Low-Power, High-Performance, Fast Fourier Transform Processor Design."
Design of the baseband transmitter, parts of the receiver, and
some system-level blocks in an 802.11a wireless LAN (54 Mbps, 5 GHz) at
SPIFFEE: an energy-efficient single-chip 1024-point FFT processor.