EEC118 - Digital Integrated Circuits
UC Davis
Dept. of Electrical and Computer Engineering

Prof. Rajeevan Amirtharajah

3173 Kemper Hall

E-mail:    ramirtha@ece.ucdavis.edu

Office Hours: Thurs 2 PM - 3 PM or by appointment.

Mackenzie Scott

E-mail:    mrscott@ucdavis.edu

Office hours: Thursdays, 3:30-5 PM in Kemper 2157/2161

Yixuan Zhai

E-mail:    yxzhai@ucdavis.edu

Office hours: Thursdays, 3:30-5 PM in Kemper 2157/2161

Lecture:

Mon/Wed 9:00 am - 10:00 am in Chemistry 176

Textbook:

Digital Integrated Circuits: A Design Perspective

J. Rabaey, A. Chandrakasan, and B. Nikolic

2nd edition

Web Page

References:

CMOS Digital Integrated Circuits: Analysis and Design

S-M. Kang and Y. Leblebici

3rd edition

CMOS VLSI Design - A Circuits and Systems Perspective

N. H. Weste and D. Harris

3rd edition

Midterm: Mon 5/3/10 in class.

Closed book, closed notes. Calculators are allowed.

Final: Tuesday June 8th, 1:00 PM to 3:00 PM, in normal lecture room (Chemistry 176)

Course web page:   http://www.ece.ucdavis.edu/~ramirtha/EEC118/S10/S10.html

The web page can also be accessed from the EEC 118 SmartSite.

Email. Please use email to contact me or the TA for your lab section only, for urgent or personal matters that cannot be handled through office hours, in-class questions, or immediately after class.

Grading

• 15%   Labs
• 15%   Design Project
• 5%   Weekly Homework
• 10%   Quizzes
• 20%   Midterm (Monday, May 3, in class)
• 35%   Final (Tuesday, June 8, 1:00 PM-3:00 PM)

Course Policies

Homework

All work must be done individually. On each homework, write your name, lab section number, and problem set number clearly at the top.

All homeworks are due Friday at 4:00 PM in Room 2131 and will be returned in your lab section after grading. Unfortunately, late homeworks cannot be accepted except for verifiable medical excuses approved by the instructor.

Each homework problem will be graded on a three-point scale: 0 (not a full effort), 1 (close but fundamental problem), and 2 (correct).

Quizzes, Midterm, and Final exam

Four announced quizzes will be given throughout the quarter. They are designed such that students that do required readings and listen in lecture will earn very high scores. Students that do not do required readings and do not listen in lecture will likely receive much lower scores. Quizzes are closed book and closed notes, although a calculator is allowed. They are designed to be completed in about 10 minutes. The lowest of the four scores will be dropped.

The midterm and final exam are mandatory components of this course. Unfortunately, no early or late exams are possible. If an unavoidable emergency prevents your attendance at the midterm or final, you will be required to submit written proof of the emergency and the make-up exam will likely be given as an oral exam with the instructor.

Course Schedule

Date	Reading	Lecture	Slides	Notes
Mon, March 29	Rabaey 1, 3 (Kang 1, 3)	Course introduction, MOSFET overview	pdf
Wed, March 31	Rabaey 3.1-3.4 (Kang 3.1-3.4)	MOS Structure and Basic Operation	pdf
Mon, April 5	Rabaey 3.3-3.5 (Kang 3.5-3.6, 5.1-5.3)	MOSFET Scaling and Capacitances Inverters	pdf
Wed, April 7	Rabaey 5.1-5.3 (Kang 5.1-5.3)	Inverters CMOS Inverters	pdf
Mon, April 12	Rabaey 5.3 (Kang 5.4)	CMOS Inverters MOS Fabrication	pdf	Quiz 1 (sol)
Wed, April 14	Rabaey 2 (Kang 2)	MOS Fabrication Inverter Transient Characteristics	pdf
Mon, April 19	Rabaey 5.4-5.5 (Kang 6.1-6.4)	Inverter Transient Characteristics
Wed, April 21	Rabaey 6.1-6.2 (Kang 7.3-7.4)	Combinational MOS Logic	pdf
Mon, April 26	Rabaey 6.2, 7.1-7.3 (Kang 8.1-8.3)	CMOS Logic Transient Characteristics	pdf	Quiz 2 (sol)
Wed, April 28	Rabaey 7.1-7.3 (Kang 8.4-8.5)	Sequential MOS Logic I	pdf
Mon, May 3	-	Midterm	Solution (pdf) Midterm Results (pdf)	EEC 118 Spring 2009 Midterm EEC 118 Spring 2009 Midterm Solutions
Wed, May 5	Rabaey 11	Arithmetic Circuits I	pdf (color)
Mon, May 10	Rabaey 11 Rabaey 6.2-6.3 (Kang 9.1-9.2)	Arithmetic Circuits II Alternative Static Logic Families I	pdf
Wed, May 12	Rabaey 6.3 (Kang 9.4-9.6)	Alternative Static Logic Families II
Mon, May 17	Rabaey 12.1-12.2 (Kang 10.1-10.2)	Alternative Static Logic Families II Dynamic Logic Circuits	pdf
Wed, May 19	Rabaey 12.1-12.2 (Kang 10.3-10.5)	Memories I	pdf	Quiz 3 (sol)
Mon, May 24	Rabaey 5.5 (Kang 6.7, 11)	Memories II Low Power CMOS Logic Circuits	pdf
Wed, May 26	Rabaey 4, 9 (Kang 6.5-6.6)	Interconnect	pdf	Quiz 4 (sol)
Mon, May 31		Memorial Day Holiday
Wed, June 2	Rabaey G, H (Kang 14)	Design for Manufacturability Alternative Logic Technologies Final Review	pdf  pdf
Tue, June 8	-	Final	Solution (pdf)	EEC 118 Spring 2009 Final EEC 118 Spring 2009 Final Solutions

Assignments

6/14/10 - Added Spring 2010 Final solution
6/03/10 - Added Spring 2009 Final solution
6/02/10 - Added Spring 2009 Final, Lectures 15, 16, and 17, and HW7 solutions
5/27/10 - Added HW7, Quiz 3 and Quiz 4 solutions
5/25/10 - Added Lectures 14
5/25/10 - Added HW6 solutions
5/17/10 - Added HW6
5/13/10 - Added Lectures 12 and 13
5/10/10 - Added midterm statistics and solutions
4/28/10 - Added Quiz 2 solutions
4/28/10 - Added Quiz 2 solutions
4/26/10 - Added Spring 2009 Midterm and solutions
4/24/10 - Added HW3 and HW4 solutions
4/22/10 - Added Lectures 9 and 11 and slides on arithmetic and project handouts
4/14/10 - Added Quiz 1 solutions
4/13/10 - Added HW2 solutions and HW4
4/08/10 - Added Lectures 5,6, 7 and 8 and HW1 solutions
4/06/10 - Added Lab 3 and HW3
4/02/10 - Added HW2
3/31/10 - Added Lectures 3 and 4, updated Lectures 1 and 2, and fixed HW1 typos
3/29/10 - Updated Lecture 1
3/28/10 - Created

Last modified 6/14/10