EEC 18 - Digital Systems I
Fall 2021

• Instructor
  Prof. Bevan Baas
  2037 Kemper Hall

• Office hours
  Labs and TA office hours meet in 2110 Kemper Hall
  
  

  	Mon	Tue	Wed	Thur	Fri
  Terry O'Neill toneill@ucdavis.edu	12:00–1:00pm	8:00am–11:50am Lab A01
  Satyabrata Sarangi ssarangi@ucdavis.edu		5:00–6:00pm	12:00pm–3:50pm Lab A03
  Dr. Baas		2:00–2:40pm		2:00–2:40pm

• Lecture
  TTh, 12:40–2:00pm

  Sign into zoom with your name as written on the course roster
  You will be checked against the course roster and admitted from a zoom waiting room
  In case of a serious connection problem: check canvas for information.
  

• Textbook
  Fundamentals of Logic Design
  C. H. Roth
  7th edition (although very similar to earlier editions, the 7th has different homework problems)

• Communication
  • Course web page:   http://www.ece.ucdavis.edu/~bbaas/18/
  • Immediately after each lecture I will be available for questions.
  • Instructor office hours.
  • TA office hours.
  • Email the TA for your lab section for urgent matters that cannot be handled during office hours, by in-class questions, in lab, or immediately after class. Please see the instructor at one of his office hours or after lecture rather than sending email.

• Grading
  • 10%   Weekly homework
  • 30%   Lab work (must be completed for course credit)
  • 15%   Quizzes (2)
  • 15%   Midterm
  • 30%   Final

• Additional course information
  • Prerequisite ENG 17 is required and waived only in unusual circumstances. Normally, an "A" or "B" grade in ECS 154A will also be sufficient.
  • The Roth text is sufficient for this course but if a second textbook is desired, I suggest: Contemporary Logic Design,, Randy H. Katz and G. Borriello, Pearson Prentice Hall.

Homework

All work must be done individually. On each homework, write your name, lab section number, and problem set number clearly at the top.

Homeworks will normally be due Friday at 4:00pm and will be returned in your lab section after grading. Unfortunately, late homeworks cannot be accepted except for verifiable medical excuses approved by the instructor.

Each major portion of each problem will be graded on a three-point scale: 0 (not a full effort), 1 (close but fundamental problem), and 2 (correct or with a very minor problem). For more challenging problems, points may be multiplied; e.g., [0,2,4 pts] or [0,3,6 pts].

Quizzes, Midterm, and Final exam

Quizzes are designed such that students that keep up with material should earn high scores. Students that do not keep up with material will likely receive much lower scores. Unless stated otherwise, potential quiz and exam topics include material covered up to and including the previous lecture, and generally emphasize material since the last quiz/midterm.

The midterm and final exam are mandatory components of this course. They are designed to test a working knowledge and understanding of concepts, not just mechanical procedures. Unfortunately, no early or late exams are possible. If an unavoidable emergency prevents your attendance at the midterm or final, you will be required to submit written proof of the emergency and the make-up exam will likely be given as an oral exam with the instructor.

Quizzes, the midterm, and the final exam will cover material from:
• Lectures,
• Assigned readings,
• Labs, and
• Homeworks.
Some material may be present in only one of these sources.


You may bring one page of double-sided hand-written (no photocopying) notes to the quizzes, midterm and final. All are otherwise closed-book and closed-notes.

The final exam is cumulative but with an emphasis on material since the midterm.

Grading Errors

Please request grading corrections within a week of being returned to you. Non-obvious or very minor grading issues will not be considered—due to fairness to all students, the inherent subjectiveness of grading which is rife with both missing-points and additional-points imperfections, and because it is physically impossible to go through submitted work of every student in minute detail (which would be required for perfect fairness). To request a regrade, submit the following to the instructor: 1) a short description of the suspected grading error, 2) the following statement on your regrade request with your signature immediately below it: "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct."

Individual work and Dishonesty

In this course, all work must be done individually—meaning done entirely by the student whose name is on the work. At the same time, discussing appropriate high-level concepts with other students are important steps in the learning process and are strongly encouraged.

The course Collaboration Policy explains the fine line between working together appropriately and inappropriately..

• We will use the Quartus design tool to synthesize verilog designs to run on the FPGAs. A free version has all the capabilities needed for this class so that is what we will use. Downloading details are given in posted handouts. Other versions which require a license are available and may appear on workstations in Kemper 2110 however the operation of the functions are the same as with the free version.
  Quartus may also be run on the linux workstations in Kemper 2107 with the command: /software/Altera/16.1/quartus/bin/quartus &

• Printing in 2110 Lab. Use the printer named "\\foa-repo-print1.ou.ad3.ucdavis.edu". Once selected, a window will pop up asking you to enter your kerberos ID and password. Once the credentials are verified, go to the printer and swipe your Aggie card to finish the printing process. The cost is $0.10/page.

  

• Each lab period has four major components:

  1. Prelab checkoff.   Except for Lab 1, prelabs are due at the beginning of the lab section. Unfortunately, points can not be given for late prelabs. They will be graded quickly on a scale from 0–5 points by your TA.

     1. Come to lab prepared to show your prelab work to your TA—likely by sharing your screen

     2. Submit your Prelab to your TA as soon as you arrive and they will be checked-off and returned in the first ~10 minutes of the period.

     3. Your TA will perform your prelab checkoff at the beginning of lab.

  2. Checkoffs of your design and simulation work must be checked off by a TA. See the Assignments table below for the week labs are due. Checkoffs should ideally be done right after the prelabs are checked but can usually be done before the end of the lab period.

     Checkoffs have three main steps:

     1. Get ready to calculate the hash, compile your design, and demonstrate it on your FPGA board

     2. Notify your TA that you are ready for your checkoff

     Checkoffs have five main steps: 1) Finalize your code and have your report ready to submit. 2) Your TA will verify the code used in your project is the same as your printed code. 3) The code is compiled and run, and you demo your design to your TA. 4) Submit your report. 5) When a lab requires you to upload your code, sometime before the end of your lab period, upload the code you wrote to canvas and you're done!

     Checkoffs are graded on the following scale (note there is no "4"):

     0   Little attempt made
     1   Not fully built
     2   All there, but not working
     3   Just about correct
     –   –
     5   Totally correct

     For several logistical reasons, you may have your designs checked off during only these time periods:

     1. your lab period,
     2. any TA's office hour, or
     3. an end-of-the-quarter special session.

  3. General lab work. Most of the lab period is spent on the current week's lab.

  4. Upload material to be submitted such as Verilog, simulation printouts, etc. must be uploaded to canvas before the end of your lab session

     Lab report requirements

• Due to the large amount of grading for TAs and the fast pace of material in lab, credit for late lab work is not possible or minimal.

  • Checkoffs: late checkoffs are normally not possible. Lab 6 may be turned in one day late for a reduction in credit of 33%. For Lab 6, checkoffs may be done in parts (up to 2 parts) and late deductions, if needed, will be calculated for each part. Late days are counted until the end of the day even if after your lab period.
  • Lab reports: late reports can not be accepted
  • Canvas uploads: the entire lab's grade will be reduced by 10% if late up to one day and reduced to zero after that. Please verify your upload to avoid penalty.
  • Incorrect canvas submissions (e.g., not matching demo code or with extraneous files) must be corrected by the student and will be considered late

• Normally TAs will not be able to debug students' circuits in detail so they are available for other students. If your TA agrees to assist you in debugging your circuit, show your TA your design materials such as block and timing diagrams first. Normally, TAs will focus on teaching debugging techniques rather than finding a particular bug in your design.

• Because TAs are almost always 100% busy in lab, you may unfortunately not attend other lab sessions.

• The labs are mandatory components of this course.

• Lab grades will be adjusted at the end of the quarter so the average grade for each section is the same—this removes unavoidable differences in grading from different TAs.

• No food or drinks are allowed in the lab. Unfortunately violations of this rule have gotten worse lately so the ECE staff is getting pretty strict on this rule. Equipment is connected to an alarm system so be careful to not move equipment which could set off the alarm.

• Take care of your FPGA board. You will need to buy a new one if you lose or break yours. They can be purchased from Terasic for $55 (plus expensive shipping) or much more from amazon.

• CAD Tool Installation and Use

  • Installing Quartus, Modelsim, and SystemBuilder

  • EEC 18 Tips and Common Errors

  • Notes on active high/low for the DE-10 Lite

  • Quartus display fix for problems such as clipped text or very small icons when using high resolution displays

• Lab circuit schematics - 3 types that you should draw for circuits you build when applicable

• Active high vs. active low

• Tips for building and debugging your circuits

Date	Reading	Lecture	Notes and Handouts
Th, Sept. 23	Unit 1	Course introduction Digital processing trends	Lecture 1 slides Lecture 1 notes
Tue, Sept. 28	Unit 2	Binary arithmetic Unsigned and signed number review	Lecture 2 Unit 1
Th, Sept. 30	Unit 3	Boolean algebra: basic operators and theorems	Lecture 3 Unit 2a
Tue, Oct. 5	Unit 4.1–4.6 Unit 5	Boolean algebra: basic operators and theorems III Sum of products Product of sums	Lecture 4 Unit 2b Unit 3 LawsAndTheoremsOfBooleanAlgebra [Roth]
Th, Oct. 7		Minterms Maxterms Incompletely specified functions	Lecture 5 Unit 4 Minterms.ppt Minterns.pdf
Tue, Oct. 12		Karnaugh Maps	Lecture 6 Unit 5
Th, Oct. 14	Unit 6 Unit 7	Quiz 1 — (zoom instructions) Karnaugh Map Extras Implicants	Lecture 7 Unit 5 Extra Handout: Adders
Tue, Oct. 19	Unit 4.7 (adders & subtracters) Unit 9.1-9.2	Minimum expressions Full adders, Ripple carry adder Multiplexers Quine-McCluskey Multi-level circuits I Functional completeness	Lecture 8 Unit 6 Unit 7
Th, Oct. 21	Unit 9	Multi-level circuits II NAND, NOR 2-level circuit conversions PLDs, PLAs, wired AND/OR	Lecture 9 Ex: Multi-level NOR Unit 8 Unit 9.6
Tue, Oct. 26		Multiplexers Buses Tri-state drivers Decoders	Lecture 10 Handout: PLA example Datasheet: CPLD example, see pgs. 15–18 Unit 9 Unit 9, muxes II
Th, Oct. 28	Unit 9.6	Encoders ROMs FPGAs Timing and hazards Clockless latches Level-sensitive latches Flip-flops	Lecture 11 Handout: clocks
Mon, Nov. 1			Office hour notes
Tue, Nov. 2		Midterm — (zoom instructions)
Th, Nov. 4	Unit 8 Unit 11	Flip-flop reset and preset Clocks Registers Efficient reset and preset Enable-able registers Accumulators	Lecture 12 Unit 11 Handout: Flip-flop reset and preset
Tue, Nov. 9	Unit 12 Unit 13	Shift registers Binary counters, General counters	Lecture 13 Unit 12
Th, November 11		Happy Veterans Day
Tue, Nov. 16	Unit 14	Quiz 2 — (zoom instructions) Analysis of sequential circuits Intro to Moore & Mealy FSMs Analysis of Moore FSMs Analysis of Mealy FSMs	Lecture 14 Unit 13
Th, Nov. 18	Unit 15	Design of FSMs Moore design example Mealy design example	Lecture 15 CounterEx.ppt Unit 14
Tue, Nov. 23	Unit 16	One-hot design example Moore vs. Mealy critical path Elimination of redundant states Implication table Efficient state assignments	Lecture 16 Handout: 7 diagrams Handout: Sync vs. Async reset & preset Unit 15
Th, November 25		Happy Thanksgiving
Tue, Nov. 30	Unit 18	Sequence detection FSM Sequential circuits using ROMs, PLAs Critical timing relationships I	Lecture 17 Handout: Variable Frequency Clocks Unit 16 Critical timing relationships
Th, Dec. 2		Critical timing relationships II adders, multipliers, shifters HDLs	Lecture 18 Unit 18 Handout: HDLs
		Extra office hours   Th, Dec 2, 10am-12pm (Terry, 2110)   Fri, Dec 3, 10am-12pm (Satyabrata, 2110)   Mon, Dec 6, 11am-1pm (Terry, 2110)   Mon, Dec 6, 2pm-3pm (Prof. Baas, zoom)
Tue, Dec. 7 8:00am–3:00pm		Last chance Lab 6 checkoffs—sign up for ONE time slot only     https://doodle.com/poll/xw473sa64kr7dnki?utm_source=poll&utm_medium=link
Th, Dec. 9 8:00am–10:00am		Final exam (zoom instructions)

Assignments

Week	Prelab due and work in Lab	Lab report due at beginning of lab section	Hwk due Friday 4pm	Homework problems   (Problems in italics have their solution in the textbook)
Sep 22 – Sep 24	No lab	–	–
Sep 27 – Oct 1	Lab 1SEP 27	–	1	Unit 1: 1, 2, 4, 5 (do subt. by adding 2's comp), 7de (2's comp only), 8, 10 Unit 2: Study Guide 1–10 (do not submit)     1, 2
Oct 4 – Oct 8	–	Lab 1	2	Unit 2: 4, 5a, 11ace, 13ac, 15b, 16a, 23bd Unit 3: Study Guide 1&5 (do not submit)     Programmed Exercises 1–5 (do not submit)     6b, 7b, 8, 18f, 21a, 29
Oct 11 – Oct 15	Lab 2	–	3	Unit 4: Study Guide 2–6 (do not submit)     1, 3, 9, 14, 20, 29 Unit 5: Study Guide 5–8 (do not submit)     Programmed Exercises 1–2 (do not submit)     3, 6, 9a, 20abc, 25cd, 33
Oct 18 – Oct 22	Lab 3OCT 14	Lab 2	–	Unit 6: Study Guide 2–4 (do not submit)     Programmed Exercise 6.1 (do not submit)     2, 3 (do not submit)
Oct 25 – Oct 29	–	Lab 3	4	Unit 7: Study Guide 1, 2, 4, 5 (do not submit)     1, 4, 7, 20a, 21b, 32 Unit 8: Study Guide 5, 6 (do not submit)     1, 2, 9, 10
Nov 1 – Nov 5	Lab 4	–	5	Unit 9: Study Guide 2–6 (do not submit)     1, 4, 8, 14, 20, 27, 32ab Unit 11: Study Guide 2b–e, 3b–c, 4b–e 5a–c, 6b–c, 7b, 8a–d (do not submit)     Programmed Exercise 11.35 (do not submit)     1, 7
Nov 8 – Nov 12	–	Lab 4	6	Unit 11: 2, 10, 11, 16, 22, 24, 26 Unit 12: Study Guide 2a–d, 3a–g, 4a–k (do not submit)
Nov 15 – Nov 19	Lab 5	–	7	Unit 12: 3, 6, 7b, 8b, 13, 17abe Unit 13: Study Guide 2–6 (do not submit)     Programmed Exercise 1 (do not submit)     7, 18
Nov 22 – Nov 26	Lab 6	Lab 5	8	Unit 13: 21 Unit 14: Programmed Exercise 1–3 (do not submit)     12, 31, 45 Unit 15: Study Guide 7, 9, 11 (do not submit)     9, 23
Nov 29 – Dec 3	–	Lab 6 Due Tue, Dec 7, 4pm	–	Unit 16: Study Guide 2, 3, 5 (do not submit)     2, 15, 23 (do not submit) Unit 18: Study Guide 1, 2 (do not submit)

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