8:00am–11:50am Lab A01
12:00pm–3:50pm Lab A03
Homeworks will normally be due Friday at 4:00pm and will be returned in your lab section after grading. Unfortunately, late homeworks cannot be accepted except for verifiable medical excuses approved by the instructor.
Each major portion of each problem will be graded on a three-point scale: 0 (not a full effort), 1 (close but fundamental problem), and 2 (correct or with a very minor problem). For more challenging problems, points may be multiplied; e.g., [0,2,4 pts] or [0,3,6 pts].
Quizzes are designed such that students that keep up with material should earn high scores. Students that do not keep up with material will likely receive much lower scores. Unless stated otherwise, potential quiz and exam topics include material covered up to and including the previous lecture, and generally emphasize material since the last quiz/midterm.
The midterm and final exam are mandatory components of this course. They are designed to test a working knowledge and understanding of concepts, not just mechanical procedures. Unfortunately, no early or late exams are possible. If an unavoidable emergency prevents your attendance at the midterm or final, you will be required to submit written proof of the emergency and the make-up exam will likely be given as an oral exam with the instructor.Quizzes, the midterm, and the final exam will cover material from:
You may bring one page of double-sided hand-written (no photocopying) notes to the quizzes, midterm and final. All are otherwise closed-book and closed-notes.
The final exam is cumulative but with an emphasis on material since the midterm.
In this course, all work must be done individually—meaning done entirely by the student whose name is on the work. At the same time, discussing appropriate high-level concepts with other students are important steps in the learning process and are strongly encouraged.
The course Collaboration Policy explains the fine line between working together appropriately and inappropriately..
We will use the Quartus design tool to synthesize verilog designs to
run on the FPGAs. A free version has all the capabilities needed for
this class so that is what we will use. Downloading details are given
in posted handouts. Other versions which require a license are available
and may appear on workstations in Kemper 2110
however the operation of the functions are
the same as with the free version.
Quartus may also be run on the linux workstations in Kemper 2107 with the command: /software/Altera/16.1/quartus/bin/quartus &
Printing in 2110 Lab. Use the printer named "\\foa-repo-print1.ou.ad3.ucdavis.edu". Once selected, a window will pop up asking you to enter your kerberos ID and password. Once the credentials are verified, go to the printer and swipe your Aggie card to finish the printing process. The cost is $0.10/page.
Each lab period has four major components:
Prelab checkoff. Except for Lab 1, prelabs are due at the beginning of the lab section. Unfortunately, points can not be given for late prelabs. They will be graded quickly on a scale from 0–5 points by your TA.
Come to lab prepared to show your prelab work to your TA—likely by sharing your screen
Submit your Prelab to your TA as soon as you arrive and they will be checked-off and returned in the first ~10 minutes of the period.
Your TA will perform your prelab checkoff at the beginning of lab.
Checkoffs of your design and simulation work must be checked off by a TA. See the Assignments table below for the week labs are due. Checkoffs should ideally be done right after the prelabs are checked but can usually be done before the end of the lab period.
Checkoffs have three main steps:
Get ready to calculate the hash, compile your design, and demonstrate it on your FPGA board
Notify your TA that you are ready for your checkoff
Checkoffs have five main steps: 1) Finalize your code and have your report ready to submit. 2) Your TA will verify the code used in your project is the same as your printed code. 3) The code is compiled and run, and you demo your design to your TA. 4) Submit your report. 5) When a lab requires you to upload your code, sometime before the end of your lab period, upload the code you wrote to canvas and you're done!
Checkoffs are graded on the following scale (note there is no "4"):
For several logistical reasons, you may have your designs checked off during only these time periods:
General lab work. Most of the lab period is spent on the current week's lab.
Upload material to be submitted such as Verilog, simulation printouts, etc. must be uploaded to canvas before the end of your lab session
Lab report requirements
Due to the large amount of grading for TAs and the fast pace of material in lab, credit for late lab work is not possible or minimal.
Normally TAs will not be able to debug students' circuits in detail so they are available for other students. If your TA agrees to assist you in debugging your circuit, show your TA your design materials such as block and timing diagrams first. Normally, TAs will focus on teaching debugging techniques rather than finding a particular bug in your design.
Because TAs are almost always 100% busy in lab, you may unfortunately not attend other lab sessions.
The labs are mandatory components of this course.
Lab grades will be adjusted at the end of the quarter so the average grade for each section is the same—this removes unavoidable differences in grading from different TAs.
No food or drinks are allowed in the lab. Unfortunately violations of this rule have gotten worse lately so the ECE staff is getting pretty strict on this rule. Equipment is connected to an alarm system so be careful to not move equipment which could set off the alarm.
Take care of your FPGA board. You will need to buy a new one if you lose or break yours. They can be purchased from Terasic for $55 (plus expensive shipping) or much more from amazon.
Quartus display fix for problems such as clipped text or very small icons when using high resolution displays
Lab circuit schematics - 3 types that you should draw for circuits you build when applicable
|Date||Reading||Lecture||Notes and Handouts|
|Th, Sept. 23||Unit 1||
Digital processing trends
Lecture 1 slides
Lecture 1 notes
|Tue, Sept. 28||Unit 2||
Unsigned and signed number review
|Th, Sept. 30||Unit 3
Boolean algebra: basic operators and theorems
|Tue, Oct. 5||Unit 4.1–4.6
Boolean algebra: basic operators and theorems III
Sum of products
Product of sums
|Th, Oct. 7||
Incompletely specified functions
|Tue, Oct. 12||
|Th, Oct. 14||
— (zoom instructions)
Karnaugh Map Extras
Unit 5 Extra
|Tue, Oct. 19||
Unit 4.7 (adders & subtracters)
Full adders, Ripple carry adder
Multi-level circuits I
|Th, Oct. 21||
Multi-level circuits II
2-level circuit conversions
PLDs, PLAs, wired AND/OR
Ex: Multi-level NOR
|Tue, Oct. 26||
Handout: PLA example
Datasheet: CPLD example, see pgs. 15–18
Unit 9, muxes II
|Th, Oct. 28||
Timing and hazards
|Mon, Nov. 1||
Office hour notes
|Tue, Nov. 2||
— (zoom instructions)
|Th, Nov. 4
Flip-flop reset and preset
Efficient reset and preset
Handout: Flip-flop reset and preset
|Tue, Nov. 9||
Binary counters, General counters
|Th, November 11||Happy Veterans Day
|Tue, Nov. 16||
— (zoom instructions)
Analysis of sequential circuits
Intro to Moore & Mealy FSMs
Analysis of Moore FSMs
Analysis of Mealy FSMs
|Th, Nov. 18||Unit 15||
Design of FSMs
Moore design example
Mealy design example
|Tue, Nov. 23||Unit 16||
One-hot design example
Moore vs. Mealy critical path
Efficient state assignments
Handout: 7 diagrams
Handout: Sync vs. Async reset & preset
|Th, November 25||Happy Thanksgiving|
|Tue, Nov. 30||Unit 18||
Sequence detection FSM
Sequential circuits using ROMs, PLAs
Critical timing relationships I
Handout: Variable Frequency Clocks
Critical timing relationships
|Th, Dec. 2||
Critical timing relationships II
adders, multipliers, shifters
|Extra office hours
Th, Dec 2, 10am-12pm (Terry, 2110)
Fri, Dec 3, 10am-12pm (Satyabrata, 2110)
Mon, Dec 6, 11am-1pm (Terry, 2110)
Mon, Dec 6, 2pm-3pm (Prof. Baas, zoom)
|Tue, Dec. 7
|Last chance Lab 6 checkoffs—sign up
for ONE time slot only
Th, Dec. 9
|Week||Prelab due and
work in Lab
|Lab report due at
beginning of lab section
|Homework problems |
(Problems in italics have their solution in the textbook)
|Sep 22 – Sep 24||No lab||–||–||
|Sep 27 – Oct 1||Lab 1SEP 27
Unit 1: 1, 2, 4, 5 (do subt. by adding 2's comp),
7de (2's comp only), 8,
Unit 2: Study Guide 1–10 (do not submit)
|Oct 4 – Oct 8||–||Lab 1||2||
4, 5a, 11ace, 13ac, 15b, 16a, 23bd
Unit 3: Study Guide 1&5 (do not submit)
Programmed Exercises 1–5 (do not submit)
6b, 7b, 8, 18f, 21a, 29
|Oct 11 – Oct 15||Lab 2||–||3||
Study Guide 2–6 (do not submit)
1, 3, 9, 14, 20, 29
Unit 5: Study Guide 5–8 (do not submit)
Programmed Exercises 1–2 (do not submit)
3, 6, 9a, 20abc, 25cd, 33
|Oct 18 – Oct 22||Lab 3OCT 14
Study Guide 2–4 (do not submit)
Programmed Exercise 6.1 (do not submit)
2, 3 (do not submit)
|Oct 25 – Oct 29||–||Lab 3||4||
Study Guide 1, 2, 4, 5 (do not submit)
1, 4, 7, 20a, 21b, 32
Unit 8: Study Guide 5, 6 (do not submit)
1, 2, 9, 10
|Nov 1 – Nov 5||Lab 4||–||5||
Study Guide 2–6 (do not submit)
1, 4, 8, 14, 20, 27, 32ab
Unit 11: Study Guide 2b–e, 3b–c, 4b–e 5a–c, 6b–c, 7b, 8a–d (do not submit)
Programmed Exercise 11.35 (do not submit)
|Nov 8 – Nov 12||–||Lab 4||6||
2, 10, 11, 16, 22, 24, 26
Unit 12: Study Guide 2a–d, 3a–g, 4a–k (do not submit)
|Nov 15 – Nov 19||Lab 5
3, 6, 7b, 8b, 13, 17abe
Unit 13: Study Guide 2–6 (do not submit)
Programmed Exercise 1 (do not submit)
|Nov 22 – Nov 26||Lab 6
Unit 14: Programmed Exercise 1–3 (do not submit)
12, 31, 45
Unit 15: Study Guide 7, 9, 11 (do not submit)
|Nov 29 – Dec 3||–||Lab 6
Due Tue, Dec 7, 4pm
Study Guide 2, 3, 5 (do not submit)
2, 15, 23 (do not submit)
Unit 18: Study Guide 1, 2 (do not submit)