|Fall 2021||EEC 18||Digital Systems I|
|Fall 2021||EEC 116||VLSI Design||Final Project winners and results|
|Winter 2022||EEC 181A||Digital Systems Design Project I|
|Winter 2022||EEC 281||VLSI Digital Signal Processing|
|Spring 2022||EEC 181B||Digital Systems Design Project II|
From 1987–89, he served as a new product engineer working on the processor for a high-end minicomputer in Hewlett Packard's Computer Systems Division, Cupertino, CA. In early 1999, he joined Atheros Communications [wikipedia] as the second full-time employee after the founders and served as a core member of the team which developed the first IEEE 802.11a (54 Mbps, 5 GHz) Wi-Fi wireless LAN solution. The chipset began shipping in volume in September of 2001 and for one and a half years was the only shipping 802.11a chipset [ISSCC 2002]. Atheros became a publicly-held company in Feb. of 2004 and was purchased by Qualcomm in 2011. In 2003, Dr. Baas joined the Department of Electrical and Computer Engineering at the University of California, Davis as an Assistant Professor. He became an Associate Professor in 2008, and a full Professor in 2015.
Dr. Baas' research interests are in the algorithms, applications, architectures, arithmetic, circuits, VLSI design, and software tools for high-performance, energy-efficient, and area-efficient computation with consideration of the challenges and opportunities of future fabrication technologies. He is interested in both programmable and special-purpose processors with an emphasis on DSP, multimedia, and embedded workloads with recent projects targeting datacenter and scientific workloads. Projects include the AsAP (Asynchronous Array of simple Processors) programmable array processor chips (36 processors, 167 processors, 1000 processors), applications, and tools; Low Density Parity Check (LDPC) decoders; Fast Fourier Transform (FFT) processors; viterbi decoders; Advanced Encryption Standard (AES) ciphers; Synthetic Aperture Radar (SAR); H.264 video codecs; Display Stream Compression (DSC) codecs; sorting and string-search engines; and machine learning engines. His group is one of very few university groups in the world that design and fabricate programmable (and configurable special-purpose) processor chips. They have designed what are believed to be the #1 and #2 highest clock rate fabricated processors ever designed in a university, and among the largest deep-submicron CMOS chips ever designed in a university.Dr. Baas was a National Science Foundation Fellow from 1990–93 and a NASA Graduate Student Researcher Fellow from 1993–96. He received the National Science Foundation CAREER award in 2006, Best Paper Award at the IEEE International Conference on Computer Design 2011, Best Student Paper Award third place at IEEE International Midwest Symposium on Circuits and Systems 2015, Best Student Paper Award third place at IEEE Asilomar 2014, "WACIest" Best-In-Session Paper at ACM/IEEE Design Automation Conference (DAC) 2010, and Best Paper nominations at IEEE Asilomar 2011 and IEEE BioCAS 2010. He supervised the research that earned the College of Engineering Zuhair A. Munir Award for Best Doctoral Dissertation Honorable Mention in 2013, and was awarded the Most Promising Engineer/Scientist Award by AISES in 2006.
From 2016–19 he was an Associate Editor for the IEEE Transactions on Circuits and Systems II. From 2016–19 he was an Associate Editor for the IEEE Transactions on VLSI Systems and from 2007–12 he was an Associate Editor for the IEEE Journal of Solid-State Circuits. • He served as Guest Editor of the Journal of Signal Processing Systems, 2019; IEEE Micro, March 2012; and IEEE Design & Test of Computers, January 2013. • He was a Visiting Professor at the University of Sydney in 2015–16; the National University of Singapore in 2016; ST Microelectronics R&D, Crolles, France in 2016; and Intel's Circuit Research Lab, Hillsboro, Oregon in 2006.
He served and is serving as: Industrial Liaison Chair of the IEEE Workshop on Signal Processing Systems (SiPS) 2018; Track Program Co-Chair of the IEEE Conference on Dependable and Secure Computing 2017; Program Committee Co-Chair of the IEEE HotChips Symposium on High-Performance Chips 2011; Parallel Architecture Co-Chair of the Design Automation Conference (DAC) 2011 Workshop on Parallel Algorithms, Programming, and Architectures; • Technical Program Committee member of the IEEE/IFIP International Conference on Very Large Scale Integration (VLSI-SoC) 2014, 2022, 2023; Technical Program Committee member of the IEEE International Conference on Omni-Layer Intelligent Systems (COINS), 2019, 2022, 2023; Technical Program Committee member of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2020, 2021; Technical Program Committee member of the IEEE International Symposium on Embedded Multicore/Many-core Systems on-Chip (MCSoC), 2023, 2022, 2020, 2019; Technical Program Committee member of the IEEE S3S (SOI-3D-Subthreshold) Conference, 2019; Technical Program Committee member of the IEEE International Conference on Omni-layer Intelligent Systems 2019; Program Committee member of the IEEE/ACM International Workshop on Network on Chip Architectures (NoCArc) 2018, 2019; Technical Program Committee member of the IEEE International Conference on ASIC (ASICON) 2017; Program Committee member of the IEEE/ACM International Workshop on Network on Chip Architectures (NoCArc) 2016, 2017; Committee member of the International Solid-State Circuits Conference (ISSCC) Student Research Preview 2012, 2013, 2014; Program Committee member of the IEEE HotChips Symposium on High-Performance Chips 2009, 2010; Technical Program Committee member of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) 2010; Technical Program Committee member of the International Conference on Computer Design (ICCD) 2004, 2005, 2007, 2008, 2009; • a member of the AISES Academic Advisory Council, and the original Technical Advisory Board of Soft Machines Inc. 2006–2016. He is a member of Tau Beta Pi, Phi Kappa Phi, Eta Kappa Nu, AISES, and a Senior Member of the IEEE.
My university web page. A short bio, and a slightly longer bio which are not kept up to date.
Dissertation, February 1999
"An Approach to Low-Power, High-Performance, Fast Fourier Transform Processor Design."
Design of the baseband transmitter, parts of the receiver, and
some system-level blocks in an 802.11a wireless LAN (54 Mbps, 5 GHz) at
SPIFFEE: an energy-efficient single-chip 1024-point FFT processor.
This work was supported by NSF, NASA-GSRP, and AISES-GE fellowships.