• Instructor
  Prof. Bevan Baas
  

• Office hours
  Labs and TA office hours meet in 2107 Kemper Hall
  
  

  	Mon	Tue	Wed	Thur	Fri
  Ziyuan Dong ziydong@ucdavis.edu	3:00pm–4:00pm		1:10pm–4:00pm Lab A01
  Luis El Srouji lzelsrouji@ucdavis.edu		6:00pm–7:00pm	4:40pm–7:30pm Lab A02
  Bevan Baas		4:30pm–open		4:30pm–open

  
  

• Lecture
  TTh, 3:10pm–4:30pm
  Online through zoom; see link on canvas
  Sign into zoom with your name as written on the course roster
  You will be checked against the course roster and admitted from a zoom waiting room
  In case of a dropped connection: check slack and canvas for information.
  

• Lab Sections
  A01: Wed, 1:10–4:00pm, TA: Ziyuan Dong
  A02: Wed, 4:40–7:30pm, TA: Luis El Srouji
  

• Textbook
  Digital Integrated Circuits, A Design Perspective
  by Rabaey, Chandrakasan, and Nikolic
  2nd edition, ISBN-13: 9780130909961

• Communication
• Course web page:   http://www.ece.ucdavis.edu/~bbaas/116/
• Email the TA for your lab section for urgent matters that cannot be handled during office hours, by in-class questions, by slack, in lab, or immediately after class. Please see the instructor at one of his office hours or after lecture rather than sending email.
• Grading: Letter
• 30%   Homework & projects (Later hwks weighted much more heavily)
• 20%   Quizzes (2)
• 25%   Final project. Done individually with a brief written report. See the past project winners and results!
• 25%   Final
• Additional course information
• Prerequisite EEC 110A is required and is waived only in unusual circumstances. EEC 18/180A is recommended.
• Suggested reference: Principles of CMOS VLSI Design, Weste and Eshraghian.

Homework/Projects

All work must be submitted at one time rather than in parts.

If the assignment is reviewed in class or solutions are made available, no credit is possible for late work. If the assignment was not reviewed in class, work may be submitted with a 1/3 reduction of remaining credit (i.e., 100% → 67% → 44% → 30% ...) per day. Unreviewed late work may be submitted with a verifiable written excuse.

Each homework sub-problem will be graded on a three-step scale: 0 (not a full effort), 1 (close but fundamental problem), and 2 (correct or with a very minor problem). For more challenging problems or those with many points, points may be multiplied, e.g., [0,2,4 pts] or [0,3,6 pts]; or graded on a similar five-step scale: 0% (not a full effort), 25% (between 0%-50%), 50% (close but fundamental problem), 75% (between 50%-100%), 100% (correct or with a very minor problem).

The Final project will be done individually and consists of the complete design of a CMOS chip including datapath, control, I/O, power distribution, clock distribution, and pad circuits.

Quizzes and Final Exam

The final exam is a mandatory component of this course. Unfortunately, no early or late exam is possible.

• Quizzes and exam(s) cover all material from assigned readings, lectures (including posted notes), homework, and projects. Some exam material may be present in only one of these sources.

• Bring several sheets of blank paper, pencils, eraser, calculator (sorry, no phones), colored pencils or pens, and one page of hand-written notes (both sides ok). No need to include specific device, material, or process data such as capacitance/area or resistivity; they will be provided to you on the exam if needed.

Wording of assignment problems

Open-ended design specifications by necessity have unspecified aspects. If the wording of a hwk/project/exam problem is unclear to you, briefly write any assumptions you make, solve accordingly, and you will receive full credit as long as your assumptions are reasonable and your solution is correct.

Grading Errors

Notify the instructor of clear and significant grading errors within a week of being returned. Due to the inherent subjectiveness of grading and to be fair to all students, only truly significant mis-grades will result in a grade change. Submit to the instructor: 1) a short description of the suspected grading error, 2) the following statement on your regrade request with your signature immediately below it: "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct." To be fair to other students, detailed regrading requests will result in a re-examination of the entire work and may result in a decrease in the total score. Note that to discourage falsified regrading, some number of all graded assignments/labs/exams will be photocopied before being returned to students.

Individual Work and Dishonesty

Unless stated otherwise, all work must be done individually—meaning done entirely by the student whose name is on the work. At the same time, discussing appropriate high-level concepts with other students are important steps in the learning process and are strongly encouraged.

The course Collaboration Policy explains the fine line between working together appropriately and inappropriately..

• Course Glossary
• Fabrication technology details
• Magic layers summary table
• Design Rules
  • DRC rule summary table
  • Special Nanometer-scale rules for EEC 116
  • Hitchhiker's guide to design rules in magic
• Wire Capacitances
• CAD Tools
• Tools, non-CAD: buy colored pens or pencils for stick diagrams. Critical colors: red, green, brown or near-brown, blue, purple.
• Working from off campus
• Available ECE machines
• video: A few basic linux commands
• CAD Environment Setup
• Starting magic and irsim
• Printing Designs
• The Magic CAD Tool
• Magic Tutorials
• Magic Macros
• A few magic tips
• The ext2sim CAD utility
• An ext2sim overview
• The IRSIM CAD Tool
• Irsim Tutorial
• Irsim Commands (9.7+)
• Irsim Man Page
• A few Irsim tips
• Tips for debugging Magic and Irsim errors
• Tips for debugging and speeding up circuits with Magic and Irsim
• Tips for finishing your work quickly
• Backing up your work

All future items are tentative. Changes are normally colored in green font.

Add these papers for readings.
Next-Gen Chips Will Be Powered From Below, IEEE Spectrum
Big Trouble in Little Interconnects, IEEE Spectrum

Date	Reading	Lecture	Notes & Slides	Assignments	Lab
Th, September 23	-	Course and VLSI introduction, VLSI fabrication technologies	• Lecture 1 slides • Lecture 1 notes	-	Lab week 0: No lab
Tue, September 28	Ch. 1	Intro II, Design styles	• Lecture 2 • Introduction II • Basic Units • 7 Basic diagrams • Basics of technologies • Chip implement methods • VLSI is like art	Read "Cramming more components onto integrated circuits," Gordon Moore, Electronics, April 19, 1965. This is the landmark paper which defined "Moore's Law."	Lab week 1: Setup environment and magic beforehand. Tutorials 1, 2, 3
Th, September 30	Ch. 2	Abstraction of complexity, Cost, yield	• Lecture 3 • Abstractions of complexity • VLSI costs	Hwk 1, problems 1 and 4 are due at 2:45pm uploaded to canvas. For problem 4, use the IEEE website to find papers from the 2021 International Solid-State Circuits Conference (ISSCC) which is widely considered the top chip conference in the world for advanced chips. Accessing the web site is free from campus or a UCD VPN. Find the table of contents by searching for: "ISSCC 2021 Table of Contents". See the Course Glossary when helpful. Some data may not be listed in papers. Tabulate chip data for all papers in Sessions: 4 (Processors), 9 (ML (machine learning) Processors from Cloud to Edge), 27 (Discrete-Time ADCs), and 30 (Non-Volatile Memories), by searching for: "2021 IEEE International Solid-State Circuits Conference" session x (with quotes) which will then return paper titles from that session. Find the actual papers (which are 1-page plus figures) by searching for the title. Note: "device" = "transistor". When available, normally click on the small red pdf icons, not links.
Tue, October 5	-	Ch 2: CMOS Fab I	• Lecture 4 • Fab materials & processes	-	Lab week 2: Tutorials 4, 5, 6
Th, October 7	Ch 3: pp. 116-117 (latchup).	CMOS Fab II, Full-custom layout, Design rules, Stick diagrams, Magic abstractions vs. GDSII,	• Lecture 5 • Photomasks • Three fab examples • Advanced metal interconnect examples • Full-custom layout & magic • Design rules • Multi‑project wafer organizations   – MOSIS, LA   – Muse Semi [notes], SanJose   – CMP, France • Stick diagrams	-
Tue, October 12	Ch 5.1-5.3.2 Ch 5.4-5.4.2	Layout guidelines,	• Lecture 6 • Magic vs. GDSII/CIF • Layout Guidelines (hand drawn)		Hwk 2, due Tue Oct 12, 2:45pm Lab week 3: Tutorials 8 and 11 (Sec. 4 only)
Th, October 14	Ch 3: pp. 104-113. Sec 4.3.2: pp. 144-146 [resis­tance]	Layout guidelines II, Nwell, pwell, and their contacts	• Lecture 7 • VLSI In The News: Undersea datacenter
Tue, October 19		Latchup, Ch 5: CMOS inverter characteristics; robustness; Fanout, fanin; FO4	• Lecture 8		Lab week 4: Simulating layout. Work through Irsim Tutorial.
Th, October 21		Quiz 1 (Zoom instructions) Performance	• Lecture 9	Read "The Fanout-of-4 Inverter Delay Metric," David Harris, et al., unpublished, ˜1997 which introduces the concept of the "FO4" delay metric.
Tue, October 26	Ch 3: Sec. 3.5 [scaling]	Ch 3: MOS resistance MOS capacitances Sheet resistance,	• Lecture 10 • Notes-ch3		Hwk 3, due Fri Oct 29, 4pm Lab week 5: Irsim simulator
Th, October 28	Ch 7: pp. 326-334, 344-346, 358-360, 368-372 [seq. circuits]	Ch 3: Scaling, Ch 7: Sequential circuits, clocking, ring oscs, latches and flip-flops	• Lecture 11	"A Better Way to Measure Progress in Semiconductors," S. Moore, IEEE Spectrum, August 2020. [pdf]
Tue, November 2	Ch 5.4.3 [overall perf.]	CMOS inverters: sizing for performance	• Lecture 12 • Flip-flop schematics	"Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions," Robert H. Dennard, et al., IEEE Journal of Solid-State Circuits, October 1974. This is the landmark paper which defined "Dennard Scaling." Read pages 257, 258, and "Cir. Perf. with Scaled..." section on pages 264–266. Skim the rest. He uses κ for what we call S.	Lab week 6: Flip-flops
Th, November 4		Chain of inverters design,	• Lecture 13 • VLSI In The News: World's Largest Chip • Chain of inverters
Tue, November 9	Ch 6: pp. 236-251, 269-271 [comb. CMOS] Ch 6: pp. 277-280 (pass-trans)	Ch 6: Combinational CMOS logic gates: static static, ratioed,	• Lecture 14 • VLSI In The News: Chip shortage and Qualcomm		Hwk 4, due in Lab and Wed 10pm Lab week 7: More complex cells
Th, November 11		Happy Veterans Day
Tue, November 16	Ch 4 (Wires)	Quiz 2 (Zoom instructions) Dynamic, pass-tranistor	• Lecture 15		Lab week 8: Sub-systems
Th, November 18	Ch 9: pp. 445-462 (pads, grids,...).	Wires I	• Lecture 16 • VLSI In The News: Nano Sheets • Wires
Tue, November 23	Sec. 9.3.2: pp. 462-464 (electro­migration). Ch 12: pp. 623-634, 657-662, skim 663-669, 672-674 (memories).	Wires II	• Lecture 17 • VLSI In The News: Samsung $17B plant in Austin, TX • OnChipInductors		Lab week 9: Registers and Full adders Hwk 5, Q4 due in Lab Nov24, Q1-Q3 due canvas 10pm Nov26
Th, November 25		Happy Thanksgiving
Tue, November 30	Ch 8: pp. 377-388, 396-406, 423 (imple­men­ta­tions). Ch H: pp. 721-737 (test).	Std cell P&R chip design Chip-level structures and issues I,	• Lecture 18 • Graphene wires • Std cell design		Lab week 10: Chip-level structures Hwk 6, due canvas 10pm Dec3.
Th, December 2		Chip-level structures and issues II, FIB edits, Spare gates, Packaging, Ref: Memories,	• Lecture 19 • Electromigration (chip issue) • FIB editing • Spare gates • Packaging • Datasheet 132-pin PGA • Ref:Memories • Ref:Multipliers
Office hour: Th Dec 2, 4:30 – 5:30 pm, Prof. Baas Office hour: Fri Dec 3, 11:00 – 12:00 pm, Luis Office hour: Sat Dec 4, 2:00 – 4:00 pm, Luis Office hour: Sun Dec 5, 9:00 – 11:00 am, Ziyuan Office hour: Mon Dec 6, 9:00 – 11:00 am, Ziyuan Office hour: Mon Dec 6, 11:00 – 12:00 pm, Luis
Tue, December 7, 3:30–5:30pm			Final exam (notes) Zoom instructions
Wed, December 8 2:00 pm: Upload electronic files to canvas due 2:00 pm–9:00 pm Functional demonstration to TA in 2107 Sign up on ONLY ONCE: https://doodle.com/poll/4m848vr6pcubzwi6?utm_source=poll&utm_medium=link https://forms.gle/5qYEAWUFnoTwhWrm8 (one day late with -1/3 penalty)			Final project

A Few Advanced Topics

• "Moore's Law: A path going forward," Holt, ISSCC, Feb 2016. This paper has great scaling data on page 4 in Figs. 1.1.1, 1.1.2, and 1.1.4


• "22 nm Next-Generation IBM System z Microprocessor," Warnock, et al., ISSCC, Feb 2015. This paper describes a monster 5.2 GHz 678 mm² 17-metal-layer 22 nm IBM 2-chip system.


• "Scaling Challenges of FinFET Architecture below 40nm Contacted Gate Pitch," Razavieh, et al., Device Research Conf., June 2017. Detailed recent paper giving an overview of FinFET transistors with gate lengths as small as 7 nm. (note 7 nm has contacted gate pitch of 48 nm which is 13.7 λ)


• "Is Dark Silicon Useful?," Taylor, et al., Design Automation Conf. (DAC), June 2012. This is the landmark paper which describes "Dark Silicon."

• A wide variety of die photos at: http://diephotos.blogspot.com/, most of which appear to be older-generation full-custom designs.

• Intel: From sand to silicon - the making of a chip

• Intel: Intel Microprocessor Hall of Fame

• Transistor counts of a large number of chips

• Zoom Into a Microchip
  Approximately 0.5 μm technology since polysilicon appears to be about half of the 1.0 μm line around time 2:08. Note that the 20 nm × 20 nm squares shown around time 2:30 could contain the length of a 20 nm transistor, but not the entire transistor itself.
  

• Sand to Silicon—the Making of a Chip (Intel)
  

• How do they make silicon wafers and computer chips? (begin at silicon ingot portion)
  

• Microscopic view of an Intel i486 (1.0 μm–0.6 μm, 16–33 MHz, 1.2 million transistors, 1989)
  

• The Making of a Chip with 22nm/3D Transistors (Intel)
  

• 32 nanometer high-k metal gate chips
  Chartered, Freescale, Infineon, and Samsung. 2007. Overview of 32 nanometer high-k metal gate chips and IBM, AMD, Chartered, Freescale, Infineon, and Samsung. 2007.
  

• SMT component sizes
  SMT component size comparisons from a classic through-hole component to SMT 0805, 0603, 0402, 0201, 01005, and other components.
  

• Takaya 9600 flying probe tester dual side
  A high-speed printed-circuit-board (PCB) "flying probe" continuity and short detector
  

• VLSI In The News: Intel 10nm
• VLSI In The News: 7nm SoC chips
  
• VlsiInTheNews, Move Over Graphene: IBM Expects Copper Interconnects to Hold the CMOS Line, November 16, 2017
• VlsiInTheNews, Hearing aid, April 15, 2008
• VlsiInTheNews
• VlsiInTheNews
• VlsiInTheNews
• VlsiInTheNews
• VlsiInTheNews, May 21, 2007