EEC 116 - VLSI Design

Fall 2023

Basic Course Information

Course Policies

Course Reference Information

Course Schedule and Assignments

All future items are tentative. Changes are normally colored in green font.

Date Reading Lecture Notes & Slides Assignments Lab
Th, September 28   - Course and VLSI introduction, VLSI fabrication technologies • Lecture 1 slides
• Slides 73-76
- Lab week 0:
No lab
Tue, October 3 Ch. 1
Intro II,
Design styles
• Introduction II
• Basic Units
• 7 Basic diagrams
• Basics of technologies
• Chip implement methods
Read "Cramming more components onto integrated circuits," Gordon Moore, Electronics, April 19, 1965. This is the landmark paper which defined "Moore's Law."
If you are unfamiliar with static CMOS gates, see the textbook pages 180, 239, 241 for the inverter, NAND, NOR.
Lab week 1:
Setup environment and magic beforehand.
Tutorials 1, 2, 3
Th, October 5 Ch. 2
Abstraction of complexity,
Cost, yield
• VLSI is like art
• Abstractions of complexity
• VLSI costs
Hwk 1, problems 1 and 4 only.
For problem 4, use the IEEE website to find papers from the 2023 International Solid-State Circuits Conference (ISSCC) which is widely considered the top chip conference in the world for advanced chips. Accessing the web site is free from campus or a UCD VPN. Find the table of contents by searching for:
"ISSCC 2023 Table of Contents". See the Course Glossary when helpful. Some data may not be listed in papers. Tabulate chip data for all papers in Sessions: 2 (Digital processors), 9 (Highlighted chip releases: digital and machine learning procs), 17 (High-speed data converters), and 33 (Non-volatile memory and compute-in-memory), by searching for:
"2023 IEEE International Solid-State Circuits Conference" session x
(with quotes) which will then return paper titles from that session. Find the actual papers (which are 1-page plus figures) by searching for the title. Note: "device" = "transistor". When available, normally click on the small red pdf icons, not links.
2:45pm: Upload to canvas.
Tue, October 10 - Ch 2: CMOS Fab I • Fab materials & processes

- Lab week 2:
Tutorials 4, 5, 6
Th, October 12 Ch 3: pp. 116-117 (latchup).
Full-custom layout, Design rules, Stick diagrams,
Magic abstractions vs. GDSII,
• Photomasks
• Three fab examples
• Advanced metal interconnect examples
• Full-custom layout & magic
• Design rules
Tue, October 17 Ch 5.1-5.3.2
Ch 5.4-5.4.2
Layout guidelines,
• Multi‑project wafer organizations
  – Muse Semi [notes], SanJose
  – CMP, France
• Stick diagrams
• Magic vs. GDSII/CIF
• Layout Guidelines
(hand drawn)
"Morris Chang: Foundry Father (TSMC)," T. Perry, IEEE Spectrum, April 2011. Lab week 3:
Tutorials 8 and 11 (Sec. 4 only)
Th, October 19 Ch 3: pp. 104-113.
Sec 4.3.2: pp. 144-146 [resis­tance]
Layout guidelines II,
  Hwk 2, due Th, Oct 19, 2:45pm
"How the Father of FinFETs Helped Save Moore's Law," T. Perry, IEEE Spectrum, April 2020.
Tue, October 24   Layout guidelines III,
Nwell, pwell, and their contacts
Ch 5: CMOS inverter characteristics I
• VLSI In The News: Undersea datacenter
  Lab week 4:
Simulating layout. Work through Irsim Tutorial.
Th, October 26   Quiz 1
Ch 5: CMOS inverter characteristics II
Tue, October 31 Ch 3: Sec. 3.5 [scaling]
Fanout, fanin; FO4
Inverter performance
Ch 3: MOS resistance
• Notes-ch3 Read "The Fanout-of-4 Inverter Delay Metric," David Harris, et al., unpublished, ˜1997 which introduces the concept of the "FO4" delay metric. Hwk 3, due Wed Nov 1, end of lab
Lab week 5:
Irsim simulator
Th, November 2 Ch 7: pp. 326-334, 344-346, 358-360, 368-372 [seq. circuits]
MOS capacitances
Sheet resistance,
Ch 3: Scaling,
Ch 7: Sequential circuits, clocking,

"A Better Way to Measure Progress in Semiconductors," S. Moore, IEEE Spectrum, August 2020. [pdf]
November 7
Ch 5.4.3 [overall perf.]
Ch 7 II: ring oscs, latches and flip-flops
• Flip-flop schematics "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions," Robert H. Dennard, et al., IEEE Journal of Solid-State Circuits, October 1974. This is the landmark paper which defined "Dennard Scaling." Read pages 257, 258, and "Cir. Perf. with Scaled..." section on pages 264–266. Skim the rest. He uses κ for what we call S. Lab week 6:

Th, November 9   CMOS inverters: sizing for performance
Tue, November 14
Ch 6: pp. 236-251, 269-271 [comb. CMOS]
Ch 6: pp. 277-280 (pass-trans)
Sizing for performance II,
Chain of inverters design,

• VLSI In The News: World's Largest Chip
• Chain of inverters
  Hwk 4, due Wed Nov 15, end of lab
Lab week 7:
Flip-flop cells

Th, November 16
Ch 4 (Wires)
Quiz 2
Ch 6: Combinational CMOS logic gates
Tue, November 21
Ch 9: pp. 445-462 (pads, grids,...).
ratioed, dynamic, pass-tranistor
• VLSI In The News: Nano Sheets
"The Nanosheet Transistor is the Next (and Maybe Last) Step in Moore's Law," P. Ye, IEEE Spectrum, July 2019. Lab week 8:
More complex cells
Th, November 23 Happy Thanksgiving 
Tue, November 28
Sec. 9.3.2: pp. 462-464 (electro­migration).
Ch 12: pp. 623-634, 657-662, skim 663-669, 672-674 (memories).
• VLSI In The News: Samsung $17B plant in Austin, TX
• Wires
• OnChipInductors
"Big Trouble in Little Interconnects," S. Moore, IEEE Spectrum, January 2023. Lab week 9:

Hwk 5, due Wed Nov 29, end of lab
Th, November 30
Ch 8: pp. 377-388, 396-406, 423 (imple­men­ta­tions).
Ch H: pp. 721-737 (test).
Std cell P&R chip design
Chip-level structures and issues I,
• VLSI In The News: Backside power in TSMC's 2nm node
• Graphene wires
• Std cell design
• Histogram: quiz 1
• Histogram: quiz 2
• Histogram: current total

"Next-Gen Chips Will Be Powered From Below," B. Cline, IEEE Spectrum, August 2021.
Tue, December 5   Chip-level structures and issues II
• VLSI In The News: Chip shortage and Qualcomm
  Lab week 10:
Chip-level structures

Hwk 6, due Wed Dec 6, end of lab
Th, December 7   FIB edits,
Spare gates,
Ref: Memories,
Ref: Multipliers,
• Electromigration (chip issue)
• FIB editing
• Spare gates
• Packaging
• Datasheet 132-pin PGA
• Ref:Memories
• Ref:Multipliers
"Single-Chip Processors Have Reached Their Limits (Chiplets)," M. Smith, IEEE Spectrum, April 2022.
Office hour: Fri Dec 8 12:30-1:30, Prof. Baas, Kemper 2037
Office hour: Sat Dec 9 1-2pm, Madan, Kemper 2107
Office hour: Mon Dec 11 1-2pm, Prof. Baas, Kemper 2107
Office hour: Tue Dec 12 2-3pm, Madan, Kemper 2107
Wed, December 13, 8:00am–10:00am Final exam
Th, December 14
10:00 am: Deadline to upload files to canvas
10:00 am–6:30 pm Functional demonstration to TA in 2107, last chance
Sign up ONLY ONCE: Reservation spreadsheet.
Final project

A Few Advanced Topics

Some Interesting Images and Videos

Todo: PCB, pick and place, soldering Random previous VLSI In The News items:

EEC 116 | B. Baas | ECE Dept. | UC Davis
Last update: January 17, 2024 01:41 AM