EEC 116 - VLSI Design
Final Project Winners



Fall 2013


See your name here!


Fall 2012


Results to be posted in early October 2013!


Fall 2010
Project:
This project requires the design and layout of a datapath for a simple 8-bit processor that performs five basic operations, has two enable-able output registers, and two individually-controllable input ports. The circuits of the chip are shown below. The inputs are: a 16-bit in, and single bit clear, and clk. The outputs are 16-bit max, min, and acc. Operation of the chip begins by setting clear=1 for at least one cycle to clear all three outputs. The output acc is the accumulated sum, max is the current maximum, and min is the current minimum of all inputs since the last clearing operation.



Chips include clock trees, power rings and grid, Vdd/Gnd/input/output I/O pads with the output pad sufficient for driving a 10 pF load. Students produced all layout themselves. The chips were laid out using TSMC's 0.18 μm CMOS and scalable design rules.

Block diagram (chip)
Block diagram (top)
Overall class area x delay
Overall class chip-core area
Min: 17,036 μm2
Max: 682,683 μm2
Median: 52,622 μm2
Ratio max/min: 40.1!
Overall class delay
Min: 0.95 ns
Max: 12,490 ns
Median: 28.40 ns
Ratio max/min: 13,147!
First place winners
  Chip core Entire chip
Sean Burkhardt-Corcoran
Mohammad Amin Heydari

Core Area x Delay = 16,116 μm2⋅ns

Core Area = 17,036 μm2

Core Delay = 0.95 ns
[core] [chip]
Second place winners
  Chip core Entire chip
Val Apgar
Matthew Spriggs

Core Area x Delay = 242,062 μm2⋅ns

Core Area = 52,622 μm2

Core Delay = 4.60 ns
[core] [chip]
 
Winter 2010
Project:
The purpose of this project is to lay out the major portions of a simple digital chip that accumulates and finds the maximum and minimum of a series of input numbers. The circuits of the chip are shown below. The inputs are: a 16-bit in, and single bit clear, and clk. The outputs are 16-bit max, min, and acc. Operation of the chip begins by setting clear=1 for at least one cycle to clear all three outputs. The output acc is the accumulated sum, max is the current maximum, and min is the current minimum of all inputs since the last clearing operation.



Chips include clock trees, power rings and grid, Vdd/Gnd/input/output I/O pads with the output pad sufficient for driving a 10 pF load. Students produced all layout themselves. The chips were laid out using TSMC's 0.18 μm CMOS and scalable design rules.

Block diagram (chip)
Block diagram (top)
Overall class area x delay
:Overall class area
Min: 43,500 μm2
Max: 334,000 μm2
Ratio max/min: 7.7
:Overall class delay
Min: 2.20 ns
Max: 50.0 ns
Ratio max/min: 22.7
First place winners
  Chip core Entire chip
Brian Zimmer
Ritesh Patel

Core Area x Delay = 201,695 μm2⋅ns

Core Area = 25,275 μm2

Core Delay = 7.92 ns
[core] [chip]
Second place winners
  Chip core Entire chip
David Tu
Ivan Charcos

Core Area x Delay = 229,115 μm2⋅ns

Core Area = 37,933 μm2

Core Delay = 6.04 ns
[core] [chip]
 
2009
Project:
The purpose of this project is to design and layout a chip which contains a high-speed programmable digital filter. Filters are one of the most common blocks found in digital signal processing systems, which are increasingly popular in many electronic systems.

The filter is a 5-tap or 5-coefficient finite impulse response (FIR) filter with a saturator at its output. It processes one input sample and produces one output sample every clock cycle enabling very high data throughputs. The values of the coefficients determine the specifications and type of the filter (e.g. low-pass, high-pass, etc.) and are programmable. The filter is composed of five identical slices which each consist of three major components: 1) a multiplier, 2) an adder, and 3) registers made up of flip-flops. The slices are designed such that much longer filters can be implemented with the exact same layout by only increasing the number of slices.

Chips include clock trees, power rings and power grid, Vdd/Gnd/input/output I/O pads with the output pad sufficient for driving a 10 pF load. Students produced all layout themselves. The chips were laid out using TSMC's 0.18 μm CMOS and scalable design rules.

The two core chip plots below are shown to scale with respect to each other.

Block diagram (chip)
Block diagram (top)
Overall class area x delay
Overall class area:
Min: 43,500 μm2
Max: 334,000 μm2
Ratio max/min: 7.7
Overall class delay:
Min: 2.20 ns
Max: 50.0 ns
Ratio max/min: 22.7
First place winners
  Chip core Entire chip
Quyen Phung
Yuan Hui Li

Core Area x Delay = 152,900 μm2⋅ns

Core Area = 69,500 μm2

Core Delay = 2.20 ns
[core] [chip]
Second place winners
  Chip core Entire chip
Gary Chung
Jon Pimentel

Core Area x Delay = 165,735 μm2⋅ns

Core Area = 43,500 μm2

Core Delay = 3.81 ns
[core] [chip]
 
2008
Project:
The purpose of this project is to design and layout a chip which contains a high-speed digital low-pass filter. Filters are one of the most common blocks found in digital signal processors, which are increasingly popular in many electronic systems.

The filter is a 7-tap finite impulse response (FIR) filter and has a saturator at its output. It processes one complete sample every clock cycle enabling very high data throghputs. The filter consists of three components: 1) multipliers, 2) adders, and 3) registers made up of flip-flops. The purpose of the saturator is to clamp or saturate the filter's output from a maximum of 620 to a maximum of 255--so it fits into an 8-bit word.

The filter is highly pipelined into 7 pipeline stages. Chips include clock trees, power rings and grid, Vdd/Gnd/input/output I/O pads with the output pad sufficient for driving a 10 pF load. Students produced all layout themselves. The chips were laid out using TSMC's 0.18 μm CMOS and scalable design rules.

Datapath block diagrams: Filter and saturator, filter, multiplier.
Block diagram (chip)
Block diagram (top)
Overall class area x delay
Overall class area:
Min: 2,409,940 λ2
Max: 4,079,496 λ2
Ratio max/min: 1.7
Overall class delay:
Min: 0.34 ns
Max: 0.51 ns
Ratio max/min: 1.5
First place winners
  Chip core Entire chip
Greg Fattig
Allen Tang

Core Area x Delay = 819,379 λ2⋅ns
Core Area = 2,409,940 λ2 = 19,520 μm2

Core Delay = 0.34 ns
[core] [chip]
Second place winners
  Chip core Entire chip
Ba Duong
Yifan Liu


Core Area x Delay = 2,080,542 λ2⋅ns
Core Area = 4,079,496 λ2 = 33,044 μm2

Core Delay = 0.51 ns
[core] [chip]
 
2007
Project:
In this project, students design and layout a chip which contains an array of 100 processors that sorts a stream of 100 unsigned 8-bit numbers at very high speed. The chip uses a type of bubble sorting algorithm where data flows through 100 2-element sorting processors (rather than one processor making 100 passes through the data set as would happen in a common software implementation). If a single-issue RISC processor requires 7 cycles to perform a single comparison and swap (load, load, subtract, branch, store, store, incr_counter), to maintain the same performance as a 1.0 GHz array of processors, the RISC processor would have to run at 700 GHz!
Each processor is pipelined and includes reset and data valid input and output signals. Chips include clock trees, power rings and grid, Vdd/Gnd/input/output I/O pads with the output pad sufficient for driving a 10 pF load. Students produced all layout themselves. The chips were laid out using TSMC's 0.18 μm CMOS and scalable design rules.
Block diagram (processor and core)
Block diagram (chip)
Block diagram (top)
Overall class area x delay
Overall class area: (one processor)
Min: 379,735 λ2
Max: 4,427,821 λ2
Median: 445,176 λ2
Ratio max/min: 11.7
Overall class delay:
Min: 0.71 ns
Max: 10.00 ns
Median: 1.25 ns
Ratio max/min: 14.1
First place winners
  Chip core Entire chip
Anh Tran
Ning Xu

Core Area x Delay = 35,394,551 λ2⋅ns
Core Area = 49,851,481 λ2
Core Delay = 0.71 ns
[core] [chip]
Second place winners
  Chip core Entire chip
Khadar Shaik
Eian Vizzini

Core Area x Delay = 63,670,687 λ2⋅ns
Core Area = 50,936,550 λ2
Core Delay = 1.25 ns
[core] [chip]
2006
Project:
Full-custom histogram calculator chip which computes an 8-point histogram on an arbitrary stream of inputs with up to 255 inputs per histogram "bin". The datapath is pipelined and includes reset and read out modes, and special circuits to aid in measuring the processor's critical path. Chips include clock trees, power rings and grid, Vdd/Gnd/input/output I/O pads with the output pad sufficient for driving a 10 pF load. Students produced all layout themselves. The chips were laid out using TSMC's 0.18 μm CMOS and scalable design rules with λ = 0.09μm.
Block diagram (processor)
Block diagram (chip-level)
Overall class area x delay
Overall class area:
Min: 836,300 λ2
Max: 4,300,000 λ2
Median: 1,675,300 λ2
Ratio max/min: 5.1
Overall class delay:
Min: 1.64 ns
Max: 4.99 ns
Median: 1.96 ns
Ratio max/min: 3.1
First place winners
  Chip core Entire chip
Neil Jacklin
Kyle Piper

Core Area x Delay = 1,558,700 λ2⋅ns
Core Area = 927,800 λ2
Core Delay = 1.68 ns
[core] [chip]
Second place winners
  Chip core Entire chip
Brent Bohnenstiehl
Maggie Zhang

Core Area x Delay = 2,081,700 λ2⋅ns
Core Area = 1,062,100 λ2
Core Delay = 1.96 ns
[core] [chip]
Honorable mention (smallest area)
  Chip core Entire chip
Sam Lee
Jia Ming Mar

Core Area x Delay = 2,500,500 λ2⋅ns
Core Area = 836,300 λ2
Core Delay = 2.99 ns
[core] [chip]
2005
Project:
Full-custom chip which calculates the accumulated sum, maximum input, and minimum input of a stream of 8-bit input data. The datapath is pipelined and includes reset circuits for all three outputs. Chips include clock trees, power rings and grid, Vdd/Gnd/input/output I/O pads with the output pad sufficient for driving a 10 pF load. Students produced all layout themselves. The chips were laid out using TSMC's 0.18 μm CMOS and scalable design rules with λ = 0.09μm.
Overall class area x delay
Overall class area:
Min: 545,600 λ2
Max: 3,182,652 λ2
Median: 840,984 λ2
Ratio max/min: 5.8
Overall class delay:
Min: 0.39 ns
Max: 5.00 ns
Median: 1.31 ns
Ratio max/min: 12.8
First place winners
  Chip core Entire chip
Chi Chen
Tyrone Tracy

Core Area x Delay = 212,784 λ2⋅ns
Core Area = 545,600 λ2
Core Delay = 0.39 ns
[core] [chip]
Second place winners
  Chip core Entire chip
Brian Swenson
Matthew Kong

Core Area x Delay = 323,084 λ2⋅ns
Core Area = 547,600 λ2
Core Delay = 0.59 ns
[core] [chip]
 
 
2004
Project:
Layout for a full-custom chip which has three primary inputs: an 8-bit data word, a valid signal, and a clear signal. The circuit has a switchable output that shows one of two values: 1) the accumulation of all inputs since the last clear, and 2) the maximum value since that last clear. The datapath is pipelined and includes necessary reset circuits. Chips include clock trees, power rings and grid, Vdd/Gnd/input/output I/O pads with the output pad sufficient for driving a 10 pF load. Students produced all layout themselves. The chips were laid out using TSMC's 0.18 μm CMOS and scalable design rules with λ = 0.09μm.
Overall class area
Min: 638,448 λ2
Max: 9,037,825 λ2
Ratio max/min: 14.2
Overall class delay
Min: 5.38 ns
Max: 40.0 ns
Ratio max/min: 7.4
First place winners
     
Andy Swing
Steven Tin

Core Area x Delay = 5,209,736 λ2⋅ns
Core Area = 638,448 λ2
Core Delay = 8.16 ns
   
Second place winners
     
Andrew Luo
Sofia Hao

Core Area x Delay = 6,193,937 λ2⋅ns
Core Area = 891,214 λ2
Core Delay = 6.95 ns
   

EEC 116 | ECE Dept. | UC Davis

Last update: June 18, 2009