EEC 116 - VLSI Design
Final Project Winners

2008


See your name here!


2007
Project:
In this project, students design and layout a chip which contains an array of 100 processors that sorts a stream of 100 unsigned 8-bit numbers at very high speed. The chip uses a type of bubble sorting algorithm where data flows through 100 2-element sorting processors (rather than one processor making 100 passes through the data set as would happen in a common software implementation). If a single-issue RISC processor requires 7 cycles to perform a single comparison and swap (load, load, subtract, branch, store, store, incr_counter), to maintain the same performance as a 1.0 GHz array of processors, the RISC processor would have to run at 700 GHz!
Each processor is pipelined and includes reset and data valid input and output signals. Chips include clock trees, power rings and grid, Vdd/Gnd/input/output I/O pads with the output pad sufficient for driving a 10 pF load. Students produced all layout themselves. The chips were laid out using TSMC's 0.18 μm CMOS and scalable design rules.
Block diagram (processor and core)
Block diagram (chip)
Block diagram (top)
Overall class area x delay
Overall class area: (one processor)
Min: 379,735 λ2
Max: 4,427,821 λ2
Median: 445,176 λ2
Ratio max/min: 11.7
Overall class delay:
Min: 0.71 ns
Max: 10.00 ns
Median: 1.25 ns
Ratio max/min: 14.1
First place winners
  Chip core Entire chip
Anh Tran
Ning Xu
Core Area x Delay = 35,394,551 λ2⋅ns
Core Area = 49,851,481 λ2
Core Delay = 0.71 ns
 [core] [chip]
Second place winners
  Chip core Entire chip
Khadar Shaik
Eian Vizzini
Core Area x Delay = 63,670,687 λ2⋅ns
Core Area = 50,936,550 λ2
Core Delay = 1.25 ns
 [core] [chip]
2006
Project:
Full-custom histogram calculator chip which computes an 8-point histogram on an arbitrary stream of inputs with up to 255 inputs per histogram "bin". The datapath is pipelined and includes reset and read out modes, and special circuits to aid in measuring the processor's critical path. Chips include clock trees, power rings and grid, Vdd/Gnd/input/output I/O pads with the output pad sufficient for driving a 10 pF load. Students produced all layout themselves. The chips were laid out using TSMC's 0.18 μm CMOS and scalable design rules with λ = 0.09μm.
Block diagram (processor)
Block diagram (chip-level)
Overall class area x delay
Overall class area:
Min: 836,300 λ2
Max: 4,300,000 λ2
Median: 1,675,300 λ2
Ratio max/min: 5.1
Overall class delay:
Min: 1.64 ns
Max: 4.99 ns
Median: 1.96 ns
Ratio max/min: 3.1
First place winners
  Chip core Entire chip
Neil Jacklin
Kyle Piper
Core Area x Delay = 1,558,700 λ2⋅ns
Core Area = 927,800 λ2
Core Delay = 1.68 ns
 [core] [chip]
Second place winners
  Chip core Entire chip
Brent Bohnenstiehl
Maggie Zhang
Core Area x Delay = 2,081,700 λ2⋅ns
Core Area = 1,062,100 λ2
Core Delay = 1.96 ns
 [core] [chip]
Honorable mention (smallest area)
  Chip core Entire chip
Sam Lee
Jia Ming Mar
Core Area x Delay = 2,500,500 λ2⋅ns
Core Area = 836,300 λ2
Core Delay = 2.99 ns
 [core] [chip]
2005
Project:
Full-custom chip which calculates the accumulated sum, maximum input, and minimum input of a stream of 8-bit input data. The datapath is pipelined and includes reset circuits for all three outputs. Chips include clock trees, power rings and grid, Vdd/Gnd/input/output I/O pads with the output pad sufficient for driving a 10 pF load. Students produced all layout themselves. The chips were laid out using TSMC's 0.18 μm CMOS and scalable design rules with λ = 0.09μm.
Overall class area x delay
Overall class area:
Min: 545,600 λ2
Max: 3,182,652 λ2
Median: 840,984 λ2
Ratio max/min: 5.8
Overall class delay:
Min: 0.39 ns
Max: 5.00 ns
Median: 1.31 ns
Ratio max/min: 12.8
First place winners
  Chip core Entire chip
Chi Chen
Tyrone Tracy
Core Area x Delay = 212,784 λ2⋅ns
Core Area = 545,600 λ2
Core Delay = 0.39 ns
 [core] [chip]
Second place winners
  Chip core Entire chip
Brian Swenson
Matthew Kong
Core Area x Delay = 323,084 λ2⋅ns
Core Area = 547,600 λ2
Core Delay = 0.59 ns
 [core] [chip]
 
 
2004
Project:
Layout for a full-custom chip which has three primary inputs: an 8-bit data word, a valid signal, and a clear signal. The circuit has a switchable output that shows one of two values: 1) the accumulation of all inputs since the last clear, and 2) the maximum value since that last clear. The datapath is pipelined and includes necessary reset circuits. Chips include clock trees, power rings and grid, Vdd/Gnd/input/output I/O pads with the output pad sufficient for driving a 10 pF load. Students produced all layout themselves. The chips were laid out using TSMC's 0.18 μm CMOS and scalable design rules with λ = 0.09μm.
Overall class area
Min: 638,448 λ2
Max: 9,037,825 λ2
Ratio max/min: 14.2
Overall class delay
Min: 5.38 ns
Max: 40.0 ns
Ratio max/min: 7.4
First place winners
     
Andy Swing
Steven Tin
Core Area x Delay = 5,209,736 λ2⋅ns
Core Area = 638,448 λ2
Core Delay = 8.16 ns
    
Second place winners
     
Andrew Luo
Sofia Hao
Core Area x Delay = 6,193,937 λ2⋅ns
Core Area = 891,214 λ2
Core Delay = 6.95 ns
    
EEC 116 | EEC 116, Spring 2006 | ECE Dept. | UC Davis

Last update: July 9, 2007