# EEC 116 - Homework 5

Do work individually and show all work.

For layout, use standard magic design rules plus all of the Special Nanometer-scale rules for EEC 116.

Enter all irsim simulation commands in .cmd files so simulations can be quickly demonstrated.

Submit written work on paper by the end of your lab period on the posted due date. Demonstrate layout and simulations for problems 3 and 4 to your TA in lab--it will be graded then. Be prepared to answer questions about your work. Unfortunately, no late layout or simulation work can be accepted.

[445 points total]

1. [50 pts] An inverter with a PMOS width of 8 lambda and an NMOS width of 5 lambda has an input gate capacitance of 15 fF. The inverter must drive a chip output pad plus circuit board load with a total capacitance of 85 pF. The inverter's input signal may not be inverted at the output pad from its value at the inverter's input. Design the lowest delay circuit to connect the inverter to the output pad. Show all work.

2. [80 pts] Design circuits that calculate the following expression: out = (A | B | C) | (D & E) | F
i) draw a transistor schematic for each gate
ii) draw a stick diagram for each gate

a) [20+20 pts] With one complex static CMOS gate.

b) [10+10 pts] With one ratioed NMOS gate.

c) [10+10 pts] With one dynamic CMOS gate.

3. [80 pts] An analog circuit requires a resistor of 25,500 Ω. Design 4 separate resistor standard cells that are each made of only one of these materials: i) nwell, ii) ndiff, iii) poly, and iv) metal1. The standard cells are: 35 lambda high, with a near-minimum width, are tile-able (cells can be added one tile after another like tiles on a floor) by abutting, and make full use of the chip area occupied. Consider the resistance of all corners to be zero. Use 0.25 μm CMOS material resistance data provided in the textbook in Chapter 4. For this problem only, ignore the special 116 design rules.

a) [4 x 10 pts] Calculate the minimum cell width showing all calculations

b) [4 x 10 pts] Layout in magic without DRC violations assuming λ=0.125 μm using the normal magic setup (which is actually λ=0.18 μm).

a) [25 pts] Draw a gate-level circuit schematic [5 pts], a transistor-level circuit schematic [10 pts], and a stick diagram [10 pts] for an efficient Full Adder gate using only inverter and NOR gates, and using metal1, metal2, and metal3 (metal3 sparingly only when helpful).

b) [50 pts] Layout the cell fulladder in magic and label inputs a, b, cin and outputs sum and cout and place them so the tiles can be abutted with correct operation.
Make all NMOS transistors 6 lambda wide and all PMOS 7 lambda wide.

c) [50 pts] Simulate the fulladder cell in irsim in one simulation with all 8 possible input combinations and clearly show the inputs and correct outputs in an irsim output listing or waveform [40 pts]. State how many combinations are correct for your design [10 pts].

d) [35 pts] Using the magic "getcell" command, place 8 copies of the full adder cell into a new cell called add8, and add two series inverters to each of the eight sum signals. Each second inverter uses folded transistors with a PMOS 22 lambda wide and an NMOS 14 lambda wide. Paint small extensions onto each input, output, Vdd, and Gnd node, and place new labels with the names a0-a7, b0-b7, sum0-sum7, cin0, cout7.

e) [75 pts] Simulate the add8 cell in irsim in one simulation with the following input combinations and clearly show the inputs and correct outputs sum and cout7 in an irsim output listing or waveform [65 pts]. State how many tests are correct [10 pts].

```a = 00000000, b = 00000000, cin0 = 0
a = 00000000, b = 00000000, cin0 = 1
a = 00000001, b = 00000001, cin0 = 1
a = 00000101, b = 00001011, cin0 = 0
a = 00000001, b = 00111111, cin0 = 0
a = 11111111, b = 00000001, cin0 = 0
a = 11111111, b = 00000000, cin0 = 1
a = 00000001, b = 11111111, cin0 = 0
a = 00000000, b = 11111111, cin0 = 1
```

EEC 116 | B. Baas | ECE Dept. | UC Davis
```2023/11/17  Posted
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