# EEC 116 - Homework 3

You should have already gone through the assigned magic and irsim tutorials.

Write solutions to problems not involving layout on paper and turn them in to your TA before the end of your lab period.

For problems requiring layout, 1) Follow rules #1 and #3 of the Special Nanometer-scale Rules for EEC 116. 2) Route signals in ndiff or pdiff for short distances only. 3) Resist the temptation to look at layout on the internet or from other sources (it will be obvious to me if you do). This is one of the few assignments where the density of your layout does not matter and only the correct connections matter. You will learn far more and layout guidelines will stick in your mind much better if you do your layout (in terms of sizing, location, orientation, routing material, etc.) in whatever way makes the most sense to you. There will be plenty of time for compact and regular layout throughout the quarter.

Layout and simulations will be demonstrated to your TA in lab and graded then. Be prepared to answer questions about your work. Unfortunately, no late layout work can be accepted.

Enter all irsim simulation commands in .cmd files so simulations can be quickly demonstrated.

110 total points.

1. [10 pts] a) A processor is to be fabricated in a 0.18 μm technology on 300 mm wafers which cost \$2750 each. Your company's marketing group says the die cost must be no more than \$23 per chip. Assume α = 3, and there are 0.7 defects/cm2. What is the maximum possible die size in mm2? (Writing some simple matlab code may be an easy way to find the solution.)

2. [10+10 pts] Design an 8-bit zero detector whose output goes high when all 8 inputs are low. Draw a gate-level circuit schematic [2 pts], a transistor-level circuit schematic [4 pts], and a stick diagram [4 pts] for both circuits.

i) one built with an 8-input NOR gate, and

ii) one built with three 3-input NAND gates (with inverted inputs) whose outputs go to a 3-input NOR gate. Path is Inverter→NAND→NOR.

3. [3 × 8 pts, 16 pts for half adder] Draw the schematics, stick diagrams, and layout for these circuits:
1. An inverter

2. A 2-input NOR gate

3. A 2-input NAND gate

4. A half adder made with only NAND gates and an inverter. Use an inverter for "NAND5" in the schematic.

Place labels on the following nodes:
• Vdd (power)

• GND (ground)

• Inputs: A (inverter); B and C (2-input NOR); D and E (2-input NAND); F and G (half adder).

• Outputs: S, T, U, [sum & carry] respectively

Points:
• Transistor-level schematic (turn in on paper) [2 pts each],

• Stick diagram (turn in on paper) [2 pts each],

• Layout (show your TA) [4 pts each]:

4. [40 pts] Simulate your half adder from the previous problem in irsim showing correct operation under all four input combinations. Show the inputs, all internal nodes between gates (not between transistors), and outputs on an analyzer waveform plot.

EEC 116 | B. Baas | ECE Dept. | UC Davis
```2023/10/26  Posted
2023/10/31  only 116 design rules #1 and #3 are necessary
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