EEC 116 - Homework 3

You should have already gone through the assigned magic and irsim tutorials.

Write solutions to problems not involving layout (e.g., schematics and stick diagrams) on paper, then scan and upload to canvas to submit. Submit a single pdf file to canvas clearly ordering and labeling each problem.

For problems requiring layout, 1) Follow rules #1 and #3 of the Special Nanometer-scale Rules for EEC 116. 2) Route signals in ndiff or pdiff for short distances only. 3) Resist the temptation to look at layout on the internet or from other sources (it will be obvious to me if you do). This is one of the few assignments where the density of your layout does not matter and only the correct connections matter. You will learn far more and layout guidelines will stick in your mind much better if you do your layout (in terms of sizing, location, orientation, routing material, etc.) in whatever way makes the most sense to you. There will be plenty of time for compact and regular layout later in the quarter.

Simulation will be demonstrated to your TA in lab and graded then. Be prepared to answer questions about your work. Unfortunately, no late simulation work can be accepted.

Enter all irsim simulation commands in .cmd files so simulations can be quickly demonstrated.

100 total points.

1. Draw the transistor-level schematics, stick diagrams, and layout for these circuits:

   1. [5 pts] An inverter

   2. [10 pts] A 2-input NOR gate

   3. [10 pts] A 2-input NAND gate

   4. [30 pts] A half adder made with only NAND gates and an inverter. Use an inverter for "NAND5" in the schematic.

   Place labels on the following nodes:

   • Vdd (power)

   • GND (ground)

   • Inputs: A (inverter); B and C (2-input NOR); D and E (2-input NAND); F and G (half adder).

   • Outputs: S (inverter), T (NOR), U (NAND), [sum & carry] (half adder)

   Point breakdown.

   • Schematic [20% of pts]

   • Stick diagram [20% of pts]

   • Layout [60% of pts]

2. [45 pts] Simulate your half adder from the previous problem in irsim showing correct operation under all four input combinations. Show the inputs, all internal nodes between gates (not between transistors), and outputs on the analyzer's waveform plot.

2026/10/15  Posted
2026/10/22  Clarified points for problem 1.