EEC 116 Glossary of Technical Terms

Terms and acronyms commonly used in EEC 116.

ASIC (Application-Specific Integrated Circuit)

A chip designed for a specific application. (as opposed to a chip such as a generic memory chip or a general-purpose processor, for example)

chiplet

A single chip typically smaller than it would otherwise be due to the fact it is designed to be combined with other chiplets inside a single package.

CMP (Chemical Mechanical Planarization or Chemical Mechanical Polishing)

A step in the fabrication process which results in an extremely flat chip surface.

device

Normally refers to a single transistor (NMOS or PMOS). Depending on the context, it may also refer to a single die.

die or chip

A single semiconductor integrated-circuit which is typically placed inside a package.

diffusion

Normally refers to ndiffusion and/or pdiffusion.

DRC (Design Rule Check)

Computer program (or part of a CAD program) used to check design rules of layout.

DSM (Deep Sub-Micron)

Semiconductor fabrication technologies with minimum feature sizes well below 1 micrometer (micron). Very roughly includes technologies below 0.25 um.

electromigration

Damaging effect on metal wires under high current conditions, which causes the movement of metal atoms and the possible eventual open-circuit or short-circuit failure of the wire. The effect is accelerated by uni-directional current and high temperature.

fabrication technology (or technology)

The name given to the set of processes utilized to fabricate an integrated circuit. This name either consists of or includes the minimum feature size achievable by the manufacturing process. (e.g., "14nm technology" or "22nm CMOS")

Fin-FET

A type of MOSFET field-effect transistor (FET) distinguished by a transistor channel that is on top of the substrate rather than embedded within it, and the channel is surrounded by the gate on three sides (typically).

flip-flop

A memory element. Normally used to describe only edge-triggered memory elements. (Rabaey uses the term to refer to any bistable component formed by cross-coupled gates.)

irsim

CAD tool for switch-level circuit simulation; originally developed at Stanford.

latch

A memory element. Normally used to describe transparent (i.e., when the clock is at its active level) memory elements.

magic

CAD tool for full-custom chip layout; originally developed at UC Berkeley.

metal

Term used to refer to any of the metallic "upper" interconnect layers in an integrated circuit. Layers are typically made of aluminum or more recently, copper. Advancing generations typically contain more metal layers. For example, 0.25µm / typically has 5 metal layers, 0.18µm / 6 layers, 0.13µm / 8 layers, IBM 90nm / 12 layers, Intel 14nm / 13 layers.

NMOS (N-type MOS)

N-channel MOS transistor.

ndiffusion (or ndiff)

The heavily-doped n-type part of an NMOS transistor making up the transistor's source and drain.

NoC (Network on Chip)

A communication network contained on a chip.

oxide

A compound of oxygen with another element. Normally refers to silicon dioxide in the context of integrated circuits.

package

A physical chip carrier designed to protect and provide electrical connections to the chip inside it.

PMOS (P-type MOS)

P-channel MOS transistor.

pdiffusion (or pdiff)

The heavily-doped p-type part of an PMOS transistor making up the transistor's source and drain.

poly (polysilicon or polycrystalline silicon)

Material made of polycrystalline silison (neither perfectly crystalline nor amorphous) commonly used as the gate for modern MOS transistors.

register

A memory element. Normally used to refer to either a latch or flip-flop. (Rabaey uses the term to refer to only edge-triggered memory elements.)

sheet resistance

Resistance of a material with an assumed resistivity (ρ) and thickness. Uses units of Ω/square.

Silicon dioxide or SiO₂

An electrically-insulating material made of silicon and oxygen commonly used to insulate conductors and semiconductors in integrated circuits.

SoC (System on a Chip)

A chip containing complex subsystems (e.g., wireless interfaces, DRAM controllers, video processors, AI engines, etc.) commonly inter-connected by one or more networks on chip (NoC).

substrate

The silicon wafer onto which CMOS integrated circuits are built.

2005/04/02  Written
2006/04/11  Updated for Spring 2006
2013/10/21  Added CMP
2016/09/21  Formatting changes
2018/10/01  Added a few entries
2018/10/04  Added a few entries
2023/08/22  Added a few entries: FinFET, chiplet