EEC 116 - DRC Rules

Below are some of the major DRC rules needed for EEC 116 projects.

Rule   Minimum Value   Special Notes
pdiff width 3λ -
ndiff width 3λ -
ndiff-pdiff 12λ -
nwell width 12λ -
nwell-pdiff overhang 6λ -
pwell width 12λ -
pwell-ndiff overhang 6λ -
poly width 2λ Always use this width for transistor gates
poly-poly 3λ -
gate-gate 4λ Notice more than poly-poly
poly-pc 4λ -
poly-diff 1λ -
poly-gate overhang 3λ -
diff-gate overhang 4λ -
m1 width 3λ -
m1 width 3λ -
m1-m1 3λ -
pdc/ndc width 4λ The m1 to diffusion contacts
pdc/ndc-pdc/ndc 3λ Based on m1-m1
pdc/ndc-gate 1λ Diff contact to transistor gate spacing
pc width 4λ Polycontact
pc-pc 4λ Based on poly-pc
m2 width 3λ -
m2-m2 4λ -
m2c width 5λ -
m2c-m2c 4λ Based on m2-m2
m3 width 3λ -
m3-m3 4λ -
m3c width 5λ -
m3c-m3c 4λ Based on m3-m3


EEC 116 | B. Baas | ECE Dept. | UC Davis
2010/10/08  Written (Trevin Murakami)