|All work must be done individually. If the assignment is reviewed in class or solutions are made available, no credit is possible for late work. If the assignment was not reviewed in class, work may be submitted with a 1/3 reduction of remaining credit (i.e., 100% -> 67% -> 44% -> 30% ...) per day. Unreviewed late work may be submitted with a verifiable written excuse. Each homework sub-problem will be graded on a three-step scale: 0 (not a full effort), 1 (close but fundamental problem), and 2 (correct or with a very minor problem). For more challenging problems or those with many points, points may be multiplied, e.g., [0,2,4 pts] or [0,3,6 pts]; or graded on a similar five-step scale: 0% (not a full effort), 25% (between 0%-50%), 50% (close but fundamental problem), 75% (between 50%-100%), 100% (correct or with a very minor problem).|
|Notify the instructor of clear and significant grading errors within a week of being returned. Due to the inherent subjectiveness of grading and to be fair to all students, only truly significant mis-grades will result in a grade change. Submit to the instructor: 1) a short description of the suspected grading error, 2) the following statement on your regrade request with your signature immediately below it: "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct." To be fair to other students, detailed regrading requests will result in a re-examination of the entire work and may result in a decrease in the total score. Note that to discourage falsified regrading, some number of all graded assignments/labs/exams will be photocopied before being returned to students.|
|Th, Sept 22||-||Course and VLSI introduction, VLSI fabrication technologies||
Letter grade assignments
|No lab this week|
|Tue, Sept 27||
||Abstraction of complexity, design styles||Lecture02||Read "Cramming more components onto integrated circuits," Gordon Moore, Electronics, April 19, 1965.|
|Th, Sept 29||
Ch 2: CMOS Fab I
Hwk 1, problems 1 and 4.
For problem 4, use the IEEE website to find the 2016 International Solid-State Circuits Conference (ISSCC) proceedings. Accessing the web site requires a subscription but is free from campus. The ISSCC is widely considered the top chip conference in the world for advanced chips. The conference's Advance Program gives a nice summary of the sessions and paper abstracts.
For this homework, use chips from only Sessions: 4 (Digital Processors), 7 (Nonvolatile Memory Solutions), 9 (High-Performance Wireless), and 15 (Oversampled Data Converters), by searching for "Solid-State Conference 2016 session x" which will then give you the paper titles from that session. It is then very easy to get copies of the papers (which are 1-page plus figures) by searching on the title.
Due at the beginning of class (3:10pm)
(These notes are probably not needed for this problem: "International Solid-State Circuits Conference Table of Contents". Browse > Conference Publications > select 2016 > select IEEE > scroll down to find "Solid-State Circuits (ISSCC), IEEE International Conference")
|Tue, October 4||-||
CMOS Fab II,
Full-custom layout, Stick diagrams
Layout & magic
|Th, October 6||
Ch 3: pp. 116-117 (latchup).
||Layout guidelines I||
|Tue, October 11||
Ch 5.1-5.3.2, 5.4
Layout guidelines II,
nwell and pwell, Latchup,
Ch 5: CMOS inverter characteristics I: reliability
|Th, October 13||
Ch 3: pp. 104-113.
Sec 4.3.2: pp. 144-146 (resistance)
Ch 3: MOS resistance, capacitances
Due anytime during lab, Friday, October 14
|Tue, October 18||
Ch 3: Sec. 3.5
Ch 3: Scaling
Ch 7: Sequential circuits, clocking
|Th, October 20||
Ch 7: pp. 326-334, 344-346,
||Ch 7: Sequential circuits II: ring oscs, latches and flip-flops||Flip-flop schematics|
|Tue, October 25||-||
Sequential circuits III,
CMOS inverters: sizing for performance
|Th, October 27||
Ch 6: pp. 236-251, 269-271
Ch 6: pp. 277-280
Chain of inverters design,
Ch 6: Combinational CMOS logic gates
Due anytime during lab
|Tue, November 1||Midterm
Covers all material discussed or assigned through Oct 25 and Hwk 3
|Th, November 3||
Ch 6: ratioed logic, dynamic logic,
|Th, November 8||
Ch 4 (all)
pass transistor logic
Ch 4: Wires I
Due during lab
|Tue, November 10||-||Wires II||
|Fri, November 11||Veterans Day
|Tue, November 15||
Ch 12: pp. 623-638, 657-669, 672-674
Ch 12: Memories I,
|Th, November 17||
Ch 9: pp. 445-462 (pads, grids,...).
Chip-level structures and issues I,
Due at the beginning of lecture.
|Tue, November 22||
Sec. 9.3.2: pp. 462-464 (electromigration).
Chip-level structures and issues II,
|Th, November 24||Happy Thanksgiving
|Tue, November 29||
Ch 8: pp. 377-388, 396-406,
Ch H: pp. 721-737 (test).
Power dissipation and thermal limits,
Std cell P&R chip design example
Datasheet 132-pin PGA,
Std cell design
VLSI design is like artwork
Due during lab. Use command file script.
|Th, December 1||
|xxx, December xx
Electronic upload by beginning of checkoff
Checkoff: sign up on doodle poll
Electronic files uploaded to smartsite, paper submission and functional demonstration to TA in lab.
|Wed, December 7, 1:00-3:00pm||Final exam