EEC 116 - VLSI Design

Fall 2010

Course Information

Instructor
Prof. Bevan Baas
2037 Kemper Hall
Office hours:

Tue 12pm after lecture (1130 Bainer)
Tue 2-3pm
Wed 12-1pm
Thur 12pm after lecture (1130 Bainer)

Lecture
TTh, 10:30am-12:00pm
1130 Bainer

Lab
Wed, 6-9pm
2107 Kemper Hall

Textbook
Digital Integrated Circuits, A Design Perspective
by Rabaey, Chandrakasan, and Nikolic
2nd edition

Teaching Assistant

Trevin Murakami, tmurakami@ucdavis.edu
Office Hours:
- Fri 1-2pm, 2107 Kemper
- Wed lab 6-9pm (except when lab is not scheduled)

Communication

Course web page: http://www.ece.ucdavis.edu/~bbaas/116/
Email: Please see the instructor at one of his office hours or after lecture rather than send email. The TA is available to assist with urgent matters that cannot be handled via office hours, in-class questions, or immediately after class.

Grading: Letter

35% Homework & projects (Later hwks weighted much more heavily)
15% Midterm
25% Final project. Done in groups of 2 with a brief written report
Project winners and results!
25% Final

Additional course information

Prerequisites: EEC 110A and EEC 180A
Suggested reference: Principles of CMOS VLSI Design, Weste and Eshraghian.

Course Glossary

Fabrication technology and glossary

Magic layers summary table
Design Rules
- MOSIS Scalable Design Rules
  See section 2.4 for details on "SCMOS_DEEP" which we will be using in EEC 116.
- DRC rule summary table
- Special DRC rules for EEC 116
- Hitchhiker's guide to design rules in magic
Wire Capacitances

CAD Tools

Tools, non-CAD: buy colored pens or pencils for stick diagrams. Critical colors: red, green, brown or near-brown, blue, purple. Use for some hwks and projects, bring to exams.
Environment Setup
Available ECE machines
Printing Designs
Working at Home
The Magic CAD Tool

The IRSIM CAD Tool

Irsim Tutorial
Irsim Commands (9.7+)
Irsim Man Page
Example irsim cmd files: 1clk.cmd, example.cmd, assume your clock signal is called "clock".

Notes on installing the magic and irsim CAD tools
Tips for debugging and avoiding problems with Magic and Irsim
Backing up your work

Some interesting references

Course Policies

Homework/Projects

All work must be done individually.

If the assignment is reviewed in class, no credit is possible for late work. If the assignment was not reviewed in class, work may be submitted with a 1/3 reduction of remaining credit (i.e., 100% -> 67% -> 44% -> 30% ...) per day. Unreviewed late work may be submitted with a verifiable written medical excuse.

Each homework sub-problem will be graded on a three-step scale: 0 (not a full effort), 1 (close but fundamental problem), and 2 (correct or with a very minor problem). Problems with many points are graded on a similar five-step scale: 0% (not a full effort), 25% (between 0%-50%), 50% (close but fundamental problem), 75% (between 50%-100%), 100% (correct or with a very minor problem).

Midterm and Final Exam

Both exams cover all material from assigned readings, lectures (including posted notes), homework, and projects. Note that some material may be present in only one of these sources.
The Midterm exam covers all material from before the midterm date.
The Final exam is cumulative but with an emphasis on material since the midterm. It will be similar to the midterm but slightly more difficult.
Bring pencils, eraser, calculator, colored or pencils pens, and one page of hand-written notes (both sides ok).

Grading Errors

Notify the instructor of clear and significant grading errors within a week of being returned. Due to the inherent subjectiveness of grading and to be fair to all students, only truly significant mis-grades will result in a grade change. Frivolous regrading requests will result in a re-examination of the entire work and may result in a decrease in the total score. Submit to the instructor: 1) a short description of the suspected grading error, 2) the following statement on your regrade request with your signature immediately below it: "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct." Note that to discourage falsified regrading, some number of all graded assignments/labs/exams will be photocopied before being returned to students.

Individual Work and Dishonesty

In this course, all work must be done "individually"—meaning done entirely by the student whose name is on the work. However, asking other students conceptual questions and explaining high-level concepts are important steps in the learning process and are strongly encouraged. This is very different from giving or receiving aid related to a specific assigned problem—which is not permitted. Copying someone else's work or allowing your work to be copied in any setting (hwk, lab, exams,...) does not promote learning, is unfair to honest students, and will be immediately reported to Student Judicial Affairs. Students that observe inappropriate activity should report what they see (anonymously if desired) to a TA or the instructor.

Collaboration Policy

Unclear wording on assignments

My rule on hwk/project wording is that I will stick with what I have written as long as it is reasonable, even if it isn't quite what I intended. If unclear wording caused you to pursue a different solution, talk to me and if your interpretation is reasonable, I will work something out. Talking to me well before the due date will be far better.

Course Schedule and Assignments

All future items are tentative.

Date Reading Lecture Slides Assignments

Th, September 23 - Course and VLSI introduction Lecture01 Read "Cramming more components onto integrated circuits," Gordon Moore, Electronics, April 19, 1965.

Tue, September 28 Ch. 1 VLSI techs, abstraction of complexity, design styles, cost, yield Lecture02

Th, September 30 Ch. 2 Reliability, inverter characteristics VlsiInTheNews, high K gate dielectric Hwk 1, problems 1 and 4.
Due Th, Sept 30, 10:30pm in class.
For problem 4, use the IEEE website to find the 2010 International Solid-State Circuits Conference (ISSCC) proceedings. Use chips from only Sessions 5, 12, 15, 16, 18, and 24 by searching for "Solid-State Conference 2010 session 5". Here are the Table of Contents for the conference. Accessing the web site requires a subscription but can be accessed for free from campus. The ISSCC is widely considered the top conference for advanced chips.

Tue, October 5 - Performance, fanout, fanin, layout Lecture04

Th, October 7 Ch 3: 116-117 (Latchup) Ch 2: CMOS Fab, latchup, nwell and pwell VlsiInTheNews, Foundries
VlsiInTheNews, photomasks
Notes-fab basics
Notes-photomasks
Notes-fab examples

Tue, October 12 - Layout guidelines I Notes-layout
Notes-stick diagrams
Notes-LayoutGuidelines Hwk 2
Due at the beginning of class (10:30am)

Th, October 14 Ch 3: pg. 104-113;
Sec 4.3.2: pg. 144-6 (resistance) Layout guidelines II,
Ch 3: MOS resistance, capacitances, sheet resistance Notes-ch3

Tue, October 19 Ch 3: Sec. 3.5
Ch 3: Scaling

Th, October 21 Ch 7: pg. 326-334, 344-346, 358-360, 368-372,
Ch 7: Sequential circuits, clocking, ring oscs, latches and flip-flops Flip-flop schematics Hwk 3
Due at the beginning of class (10:30am)

Tue, October 26 Midterm (notes)

Th, October 28 Ch 5.1-5.3.2, 5.4 Ch 5: CMOS inverter characteristics I

Tue, November 2 Ch 5: CMOS inverter characteristics II

Th, November 4 Ch 6: pg. 236-251, 269-271
Ch 6: pg. 277-280 Ch 6: Combinational CMOS logic gates, pass transistor, ratioed, dynamic logic,

Tue, November 9 Ch 4 (all)
Ch 4: Wires I
Hwk 4
Due at the beginning of class (10:30pm)

Th, November 11 Veteran's Day - no lecture

Tue, November 16 - Wires II Notes-OnChipInductors

Th, November 18 Ch 9: pg. 446-462 (pads, grids,...) Pipelining
Chip-level structures and issues I
Chip-level structures and issues II Notes-Pipelining
Hwk 5
Due at the beginning of class (10:30pm)

Tue, November 23 - Electromigration,
Notes-Electromigration

Th, November 25 Thanksgiving - no lecture

Tue, November 30 Ch 12: pg. 624-638, 657-669, 672-674 Ch 12: Memories
Power dissipation and thermal limits Notes-Memories

Th, December 2 Ch 8: pg. 378-388, 396-406, 423 Sec. 9.3.2
Ch H: pg. 721-737 Std cell P&R chip design example
Packaging
Validation, testing, reliability, IC design approaches and technology trends VlsiInTheNews, hearing aid
Packaging
Datasheet 132-pin PGA VLSI design perspective
Std cell design
Hwk 6
Due at the beginning of class (10:30pm)

Wed, December 8, 1:00-3:00pm Final exam (notes) Final project
Due Tue December 7, 4:00pm in the hwk box

Some interesting videos

VLSI In The News items from 2007:

Major updates:

2010/10/29  Last update

Date	Reading	Lecture	Slides	Assignments
Th, September 23	-	Course and VLSI introduction	Lecture01	Read "Cramming more components onto integrated circuits," Gordon Moore, Electronics, April 19, 1965.
Tue, September 28	Ch. 1	VLSI techs, abstraction of complexity, design styles, cost, yield	Lecture02
Th, September 30	Ch. 2	Reliability, inverter characteristics	VlsiInTheNews, high K gate dielectric	Hwk 1, problems 1 and 4. Due Th, Sept 30, 10:30pm in class. For problem 4, use the IEEE website to find the 2010 International Solid-State Circuits Conference (ISSCC) proceedings. Use chips from only Sessions 5, 12, 15, 16, 18, and 24 by searching for "Solid-State Conference 2010 session 5". Here are the Table of Contents for the conference. Accessing the web site requires a subscription but can be accessed for free from campus. The ISSCC is widely considered the top conference for advanced chips.
Tue, October 5	-	Performance, fanout, fanin, layout	Lecture04
Th, October 7	Ch 3: 116-117 (Latchup)	Ch 2: CMOS Fab, latchup, nwell and pwell	VlsiInTheNews, Foundries VlsiInTheNews, photomasks Notes-fab basics Notes-photomasks Notes-fab examples
Tue, October 12	-	Layout guidelines I	Notes-layout Notes-stick diagrams Notes-LayoutGuidelines	Hwk 2 Due at the beginning of class (10:30am)
Th, October 14	Ch 3: pg. 104-113; Sec 4.3.2: pg. 144-6 (resistance)	Layout guidelines II, Ch 3: MOS resistance, capacitances, sheet resistance	Notes-ch3
Tue, October 19	Ch 3: Sec. 3.5	Ch 3: Scaling
Th, October 21	Ch 7: pg. 326-334, 344-346, 358-360, 368-372,	Ch 7: Sequential circuits, clocking, ring oscs, latches and flip-flops	Flip-flop schematics	Hwk 3 Due at the beginning of class (10:30am)
Tue, October 26		Midterm (notes)
Th, October 28	Ch 5.1-5.3.2, 5.4	Ch 5: CMOS inverter characteristics I
Tue, November 2		Ch 5: CMOS inverter characteristics II
Th, November 4	Ch 6: pg. 236-251, 269-271 Ch 6: pg. 277-280	Ch 6: Combinational CMOS logic gates, pass transistor, ratioed, dynamic logic,
Tue, November 9	Ch 4 (all)	Ch 4: Wires I		Hwk 4 Due at the beginning of class (10:30pm)
Th, November 11		Veteran's Day - no lecture
Tue, November 16	-	Wires II	Notes-OnChipInductors
Th, November 18	Ch 9: pg. 446-462 (pads, grids,...)	Pipelining Chip-level structures and issues I Chip-level structures and issues II	Notes-Pipelining	Hwk 5 Due at the beginning of class (10:30pm)
Tue, November 23	-	Electromigration,	Notes-Electromigration
Th, November 25		Thanksgiving - no lecture
Tue, November 30	Ch 12: pg. 624-638, 657-669, 672-674	Ch 12: Memories Power dissipation and thermal limits	Notes-Memories
Th, December 2	Ch 8: pg. 378-388, 396-406, 423 Sec. 9.3.2 Ch H: pg. 721-737	Std cell P&R chip design example Packaging Validation, testing, reliability, IC design approaches and technology trends	VlsiInTheNews, hearing aid Packaging Datasheet 132-pin PGA VLSI design perspective Std cell design	Hwk 6 Due at the beginning of class (10:30pm)
Wed, December 8, 1:00-3:00pm		Final exam (notes)		Final project Due Tue December 7, 4:00pm in the hwk box