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| All work must be done individually. If the assignment is reviewed in class or solutions are made available, no credit is possible for late work. If the assignment was not reviewed in class, work may be submitted with a 1/3 reduction of remaining credit (i.e., 100% -> 67% -> 44% -> 30% ...) per day. Unreviewed late work may be submitted with a verifiable written excuse. Each homework sub-problem will be graded on a three-step scale: 0 (not a full effort), 1 (close but fundamental problem), and 2 (correct or with a very minor problem). Problems with many points are graded on a similar five-step scale: 0% (not a full effort), 25% (between 0%-50%), 50% (close but fundamental problem), 75% (between 50%-100%), 100% (correct or with a very minor problem). |
| Notify the instructor of clear and significant grading errors within a week of being returned. Due to the inherent subjectiveness of grading and to be fair to all students, only truly significant mis-grades will result in a grade change. Frivolous regrading requests will result in a re-examination of the entire work and may result in a decrease in the total score. Submit to the instructor: 1) a short description of the suspected grading error, 2) the following statement on your regrade request with your signature immediately below it: "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct." Note that to discourage falsified regrading, some number of all graded assignments/labs/exams will be photocopied before being returned to students. |
| Date | Reading | Lecture | Slides | Assignments |
| Mon, October 1 | - | Course and VLSI introduction | Lecture01 | Read "Cramming more components onto integrated circuits," Gordon Moore, Electronics, April 19, 1965. |
| Wed, October 3 | Ch. 1 | VLSI techs, abstraction of complexity, design styles, cost, yield |
VlsiInTheNews, Foundries Lecture02 |
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| Mon, October 8 | Ch. 2 | Ch 2: CMOS Fab I |
VlsiInTheNews, high K gate dielectric Notes-fab basics Notes-photomasks Notes-fab examples |
Hwk 1, problems 1 and 4. For problem 4, use the IEEE website to find the 2012 International Solid-State Circuits Conference (ISSCC) proceedings. Use chips from only Sessions 2 (High BW DRAM & PRAM) 3 (Processors), 6 (Medical, Displays, Imagers), 10 (High-Perf Digital), 12 (Multi-Media & Comm), and 27 (Data Converters), by searching for "Solid-State Conference 2012 session x". Here are the Table of Contents for the conference. Accessing the web site requires a subscription but can be accessed for free from campus. The ISSCC is widely considered the top conference for advanced chips. Due at the beginning of class (4:10pm) |
| Wed, October 10 | - |
CMOS Fab II, Full-custom layout |
VlsiInTheNews, photomasks | |
| Mon, October 15 | Ch 3: 116-117 (Latchup) |
Latchup, nwell and pwell, Layout guidelines I |
Notes-layout Notes-stick diagrams Notes-LayoutGuidelines |
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| Wed, October 17 | - |
Layout guidelines II, Inverter characteristics: reliability, fanout, fanin |
VlsiInTheNews, Lightning chip
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Hwk 2 Due at the beginning of class (4:10pm) |
| Mon, October 22 |
Ch 3: pg. 104-113; Sec 4.3.2: pg. 144-6 (resistance) |
Ch 3: MOS resistance, capacitances, sheet resistance | Notes-ch3 | |
| Wed, October 24 |
Ch 3: Sec. 3.5 |
Ch 3: Scaling Ch 7: Sequential circuits, clocking, ring oscs, latches and flip-flops |
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| Mon, October 29 |
Ch 7: pg. 326-334, 344-346,
358-360, 368-372, |
Ch 7: Sequential circuits II | Flip-flop schematics |
Hwk 3 Due at the beginning of class (4:10pm) |
| Wed, October 31 | Midterm (notes) Covers all material discussed or assigned through Oct 24 and Hwk 3 |
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| Mon, November 5 | Ch 5.1-5.3.2, 5.4 |
Ch 5: CMOS inverter characteristics I |
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| Wed, November 7 |
Ch 6: pg. 236-251, 269-271 Ch 6: pg. 277-280 |
Ch 5: CMOS inverter characteristics II Ch 6: Combinational CMOS logic gates |
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| Mon, November 12 | Veterans Day
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| Wed, November 14 |
Ch 6: pass transistor, ratioed, dynamic logic, |
Hwk 4 Due Th, Nov 15 at 3:00pm Upload .mag files, paper copies in homework box in Kemper 2131 |
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| Mon, November 19 |
Ch 4 (all) |
Ch 4: Wires I |
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| Wed, November 21 | - | Wires II | Notes-OnChipInductors | |
| Mon, November 26 | Ch 9: pg. 446-462 (pads, grids,...) |
Pipelining, Chip-level structures and issues I |
Notes-Pipelining |
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| Wed, November 28 | - |
Chip-level structures and issues II,
Electromigration, |
Notes-Electromigration |
Hwk 5 Due at the beginning of class (4:10pm) |
| Mon, December 3 | Ch 12: pg. 624-638, 657-669, 672-674 |
Packaging, Ch 12: Memories Power dissipation and thermal limits |
Packaging, Datasheet 132-pin PGA, Notes-Memories |
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| Wed, December 5 |
Ch 8: pg. 378-388, 396-406, 423
Sec. 9.3.2 Ch H: pg. 721-737 |
Std cell P&R chip design example Validation, testing, reliability, IC design approaches and technology trends |
Std cell design VLSI design is like artwork |
Hwk 6 Due during lab session |
| Tue, December 11, 8:00-10:00am | Final exam (notes) |
Final project Due Mon December 10, |
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2012/10/02 Last update