EEC 116 - VLSI Design

Fall 2013

Course Information

Course Policies


All work must be done individually.

If the assignment is reviewed in class or solutions are made available, no credit is possible for late work. If the assignment was not reviewed in class, work may be submitted with a 1/3 reduction of remaining credit (i.e., 100% -> 67% -> 44% -> 30% ...) per day. Unreviewed late work may be submitted with a verifiable written excuse.

Each homework sub-problem will be graded on a three-step scale: 0 (not a full effort), 1 (close but fundamental problem), and 2 (correct or with a very minor problem). Problems with many points are graded on a similar five-step scale: 0% (not a full effort), 25% (between 0%-50%), 50% (close but fundamental problem), 75% (between 50%-100%), 100% (correct or with a very minor problem).

Midterm and Final Exam

Grading Errors

Notify the instructor of clear and significant grading errors within a week of being returned. Due to the inherent subjectiveness of grading and to be fair to all students, only truly significant mis-grades will result in a grade change. Frivolous regrading requests will result in a re-examination of the entire work and may result in a decrease in the total score. Submit to the instructor: 1) a short description of the suspected grading error, 2) the following statement on your regrade request with your signature immediately below it: "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct." Note that to discourage falsified regrading, some number of all graded assignments/labs/exams will be photocopied before being returned to students.

Individual Work and Dishonesty

Unclear wording on assignments

Course Schedule and Assignments

All future items are tentative.

Date Reading Lecture Slides Assignments
Mon, September 30   - Course and VLSI introduction Lecture01 Read "Cramming more components onto integrated circuits," Gordon Moore, Electronics, April 19, 1965.
Wed, October 2 Ch. 1 VLSI techs, abstraction of complexity, design styles, cost, yield VlsiInTheNews, Foundries 2007
No lab this week
Mon, October 7 Ch. 2 Ch 2: CMOS Fab I VlsiInTheNews, high K gate dielectric
Notes-fab basics
Notes-fab examples
Hwk 1, problems 1 and 4.
For problem 4, use the IEEE website to find the 2013 International Solid-State Circuits Conference (ISSCC) proceedings. Accessing the web site requires a subscription but is free from campus. The ISSCC is widely considered the top chip conference in the world for advanced chips.
Use chips from only Sessions: 3 (Processors), 12 (Nonvolatile Memory Solutions), 13 (High-Performance Wireless), and 26 (High-Speed Data Converters), by searching for "Solid-State Conference 2013 session x" which will then give you the paper titles from that session.
Due at the beginning of class (4:10pm)

(These are probably not needed for this problem: Table of Contents All conference papers: Browse > Conference Publications > select 2013 > select IEEE > scroll down to find "Solid-State Circuits (ISSCC), IEEE International Conference")

Wed, October 9 - CMOS Fab II,
Full-custom layout, Stick diagrams
VlsiInTheNews, photomasks
Notes-stick diagrams
Mon, October 14 Ch 3: 116-117 (Latchup) Latchup, nwell and pwell,
Layout guidelines I
Wed, October 16 Ch 5.1-5.3.2, 5.4
Layout guidelines II,
Ch 5: CMOS inverter characteristics I: reliability
- Hwk 2
Due during lab
Mon, October 21 Ch 3: pg. 104-113;
Sec 4.3.2: pg. 144-6 (resistance)
Fanout, fanin
Ch 3: MOS resistance, capacitances
VlsiInTheNews, Lightning chip
Wed, October 23 Ch 3: Sec. 3.5
Sheet resistance,
Ch 3: Scaling
Ch 7: Sequential circuits, clocking, ring oscs, latches and flip-flops
  Hwk 3
Due during lab
Mon, October 28 Ch 7: pg. 326-334, 344-346, 358-360, 368-372,
Ch 7: Sequential circuits II Flip-flop schematics  
Wed, October 30 - Ch 5: CMOS inverter characteristics I
  Hwk 4
Due during lab
Mon, November 4 Midterm (notes)
Covers all material discussed or assigned through Oct 28 and Hwk 4
Wed, November 6 Ch 6: pg. 236-251, 269-271
Ch 6: pg. 277-280
Chain of inverters problem
Ch 6: Combinational CMOS logic gates
Mon, November 11 Veterans Day 
Wed, November 13   Ch 6: pass transistor, ratioed, dynamic logic,
Mon, November 18 Ch 4 (all)
Ch 4: Wires I
Wed, November 20 - Wires II Notes-OnChipInductors  
Mon, November 25 Ch 9: pg. 446-462 (pads, grids,...) Wires III,
Chip-level structures and issues I
Wed, November 27 - Chip-level structures and issues II, Electromigration,
Hwk 5
Due during lab
Thu, November 28 Happy Thanksgiving 
Mon, December 2 Ch 12: pg. 624-638, 657-669, 672-674 Packaging
Datasheet 132-pin PGA,
Wed, December 4 Ch 8: pg. 378-388, 396-406, 423 Sec. 9.3.2
Ch H: pg. 721-737
Ch 12: Memories,
Power dissipation and thermal limits,
Std cell P&R chip design example
Testing, reliability
Std cell design
VLSI design is like artwork
Hwk 6
Due during lab
Th, December 12, 11:00am Final project
Electronic files uploaded to smartsite, paper submission and functional demonstration to TA in lab.
Fri, December 13, 3:30-5:30pm Final exam

Some interesting videos

Previous VLSI In The News items:

Major updates:
2013/09/30  Last update