EEC 116 - Homework 4

Do work individually and show all work.

For layout, use standard magic design rules plus all of the Special Nanometer-scale rules for EEC 116.

Enter all irsim simulation commands in .cmd files so simulations can be quickly demonstrated.

Submit written work on paper by the end of your lab period on the posted due date. Demonstrate layout and simulations for problems 6 and 7 to your TA in lab--it will be graded then. Be prepared to answer questions about your work. Unfortunately, no late layout work can be accepted.

[370 points total]

1. [10+10+10 pts] A ring oscillator contains 51 stages which are each made up of a fanout-of-5 inverter. The ring operates at 428 MHz.

a) Sketch three stages of this oscillator showing one way it could be constructed.

b) Sketch the oscillator's output voltage waveform and label the time required for one period of the waveform.

c) Calculate the propagation delay of each inverter.

2. [10+10+10 pts] Find the Req for the following 0.25 μm transistors. Describe and use a reasonable approximation method if needed.

a) NMOS W = 9 lambda, L = 2 lambda, Vdd = 2.5 V

b) Two PMOS W = 15 lambda, L = 2 lambda, Vdd = 1.5 V devices in series

c) Three PMOS W = 10 lambda, L = 2 lambda, Vdd = 1.70 V devices in parallel

3. a) [20+20 pts] All transistors in a 0.25 μm CMOS 3-input NOR gate are 10 lambda wide and 2 lambda long. Calculate the input capacitance of all inputs if Cox = 8 fF/μm2

b) If xd = 0.050 μm, what percentage of the gate capacitance is due to overlap capacitance?

4. [15+15+15 pts] The following gates contain PMOS transistors that are 1.5 times as wide as their NMOS transistors. NMOS transistors have source/drain dimensions of LS = LD = 1 μm and W = 4 μm, where LS and LD are the full source/drain length. For each, [5 pts] draw a schematic and [10 pts] write an expression for the total junction capacitance on each gate's output node in terms of Cj and Cjsw, assuming xd = 0.

a) Inverter

b) 2-input NAND

c) 3-input NOR gate

5. [45 pts] A smart phone processor is built using 65 nm fabrication technology and operates at 1.4 GHz while dissipating 7 Watts using a 0.9 V power supply. The chip is scaled to a 32 nm technology.

a) [10 pts] What speed and power consumption will the new chip likely have assuming constant-field scaling?

b) [15 pts] If the supply voltage on the new part were 1.1 V, what will the power consumption and speed be then?

c) [10+10 pts] i) What supply voltage should be used by the new part if 20% more performance is needed?
ii) At what clock frequency would the processor then operate?

6. [100 pts] Flip-flop cell. Design the positive-edge triggered, master-slave flip-flop called the "Safest Flip-Flop" in the handout posted on the course web page. Include two inverters inside each flip-flop to buffer the single clock input and generate clock_buf and clock_buf_bar (for internal cell use only). The FF's clock input must drive only one inverter and no other circuits.

• [10 pts] Draw a stick diagram for the cell.

• [40 pts] Layout the flip-flop cell in magic. Design it so it can be easily abutted (either "horizontally" or "vertically" with other FF cells so that Vdd and Gnd rails are shared).

• [50 pts] Simulate your flip flop in irsim and measure the clock-to-Q delay.

Other requirements:

• Make all Vdd and Gnd wires 8 λ wide
• Try to use only metals 1 and 2, however using small amounts of metal3 is ok.
7. [30+50 pts] Layout a cell called sff which is a synchronously-settable flip flop built by instantiating a single one of your flip flops and placing an OR gate (built with a NOR followed by an inverter) whose output is connected to the inner FF's D input and whose inputs are connected to sff's D input and a new input set (active high set).

Simulate the cell sff in irsim and show that it functions properly under all conditions.

EEC 116 | B. Baas | ECE Dept. | UC Davis
```2023/11/06  Posted
2023/11/07  Corrected submission instructions
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