EEC 116 - Homework 6

Do work individually and show all work.

For layout, use standard magic design rules plus all of the Special Nanometer-scale rules for EEC 116.

Enter all irsim simulation commands in .cmd files so simulations can be quickly demonstrated.

Submit written work on paper by the end of your lab period on the posted due date. Demonstrate layout and simulations for problems 3 and 4 to your TA in lab--it will be graded then. Be prepared to answer questions about your work. Unfortunately, no late layout or simulation work can be accepted.

[330 points total]

  1. [15+15 pts] Design a 2-input XNOR gate using transmission gate logic and only the inputs: a and b. To be extra safe, place an inverter at the input to each transmission gate, and an inverter at the final output. Give a i) transistor schematic and a ii) stick diagram.

  2. [80 pts] A 3 λ wide Aluminum metal1 wire must route a long distance across a chip fabricated in 0.25 μm CMOS. Wire data is given on pages 143 ("Al1") and 145. Use the average value when a range is given. Use the most accurate "distributed rc line" delay equation. Signal inversions can be neglected. Assume an inverter's delay is 30 ps. Your colleague is wondering if the wire can be sped up by insering an inverter in the middle of the wire's length. Help your colleague out by estimating with less than 5% error at what length the wire's delay without a repeater-inverter is equal to the delay with a repeater-inverter. Use any method you like (matlab, excel, calculator, etc.).

  3. [60 pts] The figure below shows a signal distribution network built in 0.25 μm CMOS whose features are described in Table 4.2 on page 143. All wires are 0.65 μm wide and are routed in metal2. There are loads at each of the lettered nodes in the network that are well-modeled by capacitances of the following values: A,B = 85 fF; C = 115 fF. D = 140 fF. E = 75 fF. F = 125 fF. For wire resistance, assume wires are made of Aluminium and choose and state your assumptions. 
                  1mm      4mm        3mm
     source ------+-----------+--------- E
                  |           |
              1mm |           | 1mm
                  +---- C     D
                  | 1mm
              2mm |
                  |
           2mm    |
        F --------+--------- B
                  |   3mm
              1mm |
                  A
    a) [20 pts] Draw the equivalent circuit and annotate the values of resistors and capacitors, using lumped R and C models for the network.

    b) [40 pts] Since the maximum delay in a digital system is the one that limits the clock frequency, find the maximum dominant time-constant (considering all nodes) in the network. Justify your answer.

  4. [60 pts] Design and layout the final-project's subtractor, which is a 13-bit ripple-carry adder. It need not be optimized for area or speed but must be complete and functional.

    1) [40 pts] show your layout

    2) [20 pts] demonstrate correct operation in irsim to your TA during lab checkoff for the following tests: 

       0000 0000 0000   0
 - 0000 0000 0000   0
 ----------------
   0000 0000 0000   0

   0000 0000 0001   1
 - 0000 0000 0000   0
 ----------------
   0000 0000 0001   1

   0000 0000 0000   0
 - 0000 0000 0001   1
 ----------------
   1111 1111 1111   -1

   1111 1111 1111   -1
 - 0000 0000 0001   1
 ----------------
   1111 1111 1110   -2

   0111 1111 1111   2047
 - 0000 1000 0000    128
 ----------------
   0111 0111 1111   1919

  5. [100 pts] Synthesize and Place & Route a simple test circuit which includes a 32-bit multiplier.


EEC 116 | B. Baas | ECE Dept. | UC Davis 
2023/11/30  Posted
2023/12/02  Updated problem 4 is for the subtractor.