EEC 216 Low Power Digital IC Design Handouts

Handouts

Handout 1
Lecture 1
Problem Set 1
Reading 1
Lecture 2
Lecture 3
Problem Set 2
Problem Set 2 Hspice Deck
Problem Set 2 Hspice Macros
Reading 2
Reading 3
Reading 4
Reading 5
Lecture 4
Lecture 5
Lecture 6
Problem Set 3
Problem Set 3 Hspice Deck
Reading 6
Reading 7
Lecture 7
Lecture 8
Design Project 1
Design Project 1 Hspice Deck
Lecture 8A
Lecture 9
Lecture 10
Handout 2
Handout 3
Lecture 11
Lecture 12
Lecture 13
Lecture 14
Lecture 15
Case Study 1
Design Project 2
Reading 8
Design Project 2 Shell Script
Example Final Project (slides)
Example Final Project (report)

Course Syllabus (PDF )
"CMOS Power Dissipation and Trends" (PDF )
Problems (PDF )
Chandrakasan, et al. "Low-Power CMOS Digital Design" (PDF )
"Metrics and Logic Level Power Estimation" (PDF )
"Power Estimation, Interconnect, and Architecture" (PDF )
Problems (PDF )
Hspice Deck (ps2.sp )
Hspice Macros (macros.sp )
Landman and Rabaey, "Architectural Power Analysis: The Dual Bit Type Method" (PDF )
Landman and Rabaey. "Activity-Sensitive Architectural Power Analysis" (PDF )
Nemani and Najm, "Towards a High-Level Power Estimation Capability" (PDF )
Nemani and Najm, "High-Level Area and Power Estimation for VLSI Circuits" (PDF )
"Low Power Circuits 1" (PDF )
"Low Power Circuits 2" (PDF )
"Clocking and Sequential Elements" (PDF )
Problems
Hspice Deck
Heller et al., "Cascode Voltage Switch Logic: A Differential CMOS Logic Family" (PDF )
Chu and Pulfrey, "A Comparison of CMOS Circuit Techniques: ..." (PDF )
"Low Power Interconnect" (PDF )
"Leakage" (PDF )
Specification (PDF )
Hspice Deck (dp1.sp )
"Subthreshold Circuits" (PDF )
"Energy Recovery Circuits" (PDF )
"Power Sources" (PDF )
Midterm W07 (PDF )
Midterm W08 Statistics (PDF )
"Energy Scavenging" (PDF )
"Power Electronics" (PDF )
"Thermal Design" (PDF )
"Temperature Measurement Circuits" (PDF )
"Fundamental Limits of Low Power Design" (PDF )
"Ultra Low Power DSP for Energy Harvesting Sensor Applications"
Specification (PDF )
Wang and Chandrakasan, "A 180-mV Subthreshold FFT Processor Using a Minimum Energy Design Methodology" (PDF )
Download (dp2.sh )
"M. Zhang Final Project Presentation (2006)" (PDF )
"M. Zhang Final Project Report (2006)" (PDF )



Solutions (PDF )



Solutions (PDF )









Solutions










Solutions (PDF )

HSPICE Files and Links

For information on running HSPICE on the UCD ECE department network, follow this URL: http://www.ece.ucdavis.edu/cad/hspice/index.html

This course relies on some of the freeware Predictive Technology Models from the Nanoscale Integration and Modeling (NIMO) Group at Arizona State University. You can access the nominal 45 nm model file here to include it in your Spice decks. You can also access a template for the Spice decks you turn in here .

In this class, we will assume a generic process based on the MOSIS Scalable CMOS design rules for deep submicron. The design rules are available online at: http://www.mosis.org/Technical/Layermaps/lm-scmos_scn6m.html . Use the DEEP column for the assumed layout rules.

A Perl script is available to generate HSPICE voltage sources from a bit stream can be downloaded from here: bitgen_hspice.pl . The plotting function does not work but the voltage sources will be exported correctly.