Notes on active high/low inputs/outputs for the DE-10 Lite and DE1-SoC

Department of Electrical and Computer Engineering
University of California, Davis

See the notes describing the role the "assertion level" or "activity level" of a signal plays in designing it correctly: Active high versus active low. The DE-10 Lite and DE1-SoC FPGA boards contain a number of input and output devices that are active high and some that are active low as described below.

  1. HEX 7-segment LED displays (active low)

    1. On — "0"

    2. Off — "1"

  2. LEDR LED displays (active high)

    1. On — "1"

    2. Off — "0"

  3. SW switches (active high)

    1. Up position — "1"

    2. Down position — "0"

  4. KEY push buttons (active low)
    De-bounced [DE-10 Lite User Manual, page 6, 25]

    1. Press — "0"

    2. Release — "1"


EEC 18 | B. Baas | ECE Dept. | UC Davis 
Written by Shifu Wu
2022/05/02  Added notes mentioning that specs apply to the DE1-SoC also (BB)
2020/05/02  Added de-bounced note for KEY (BB)
2020/04/13  Added activity levels (BB)
2020/04/10  Minor edits (BB)
2020/03/11  Minor updates
2020/01/22  Written