- [20 pts] A processor is to be fabricated in a 0.13 μm technology on
300 mm wafers which cost $3500 each. Your company's marketing group says
the die cost must be no more than $22 per chip. Assume a = 3, and there
are 1.0 defects/cm^2. What is the maximum possible die size in mm^2? Show
your work.
- [100 pts] Draw a gate-level circuit schematic (5 pts), a transistor-level
circuit schematic (10 pts), and a stick diagram (10 pts) for an
efficient Full Adder gate using only inverter and NOR gates,
and using metal1, metal2, and metal3 (metal3 sparingly only when helpful)
for routing.
Layout the cell fulladder in magic and label inputs a, b,
cin and outputs sum and cout and place them so the tiles can be abutted
with correct operation (50 pts). Make all NMOS transistors 4 lambda
wide and all PMOS 6 lambda wide, and both with minimum length channels.
Using the magic "getcell" command, place 8 copies of the full adder
cell into a new cell called add8, paint small extensions onto
each input, output, Vdd, and Gnd node, and place new labels with the
names a0-a7, b0-b7, sum0-sum7, cin0, cout7 (25 pts).
- [100 pts] Simulate the fulladder cell in irsim in one simulation
with all possible input combinations and clearly show the inputs and
correct outputs in an irsim output listing or waveform (40 pts). State
how many combinations are correct (10 pts).
Simulate the add8 cell in irsim in one simulation with the following input combinations and
clearly show the inputs and correct outputs sum and cout7 in an irsim output listing or waveform
(40 pts). State how many tests are correct (10 pts).
a = 00000000, b = 00000000, cin0 = 0
a = 00000000, b = 00000000, cin0 = 1
a = 00000001, b = 00000001, cin0 = 1
a = 00000101, b = 00001011, cin0 = 0
a = 00000001, b = 00111111, cin0 = 0
a = 11111111, b = 00000001, cin0 = 0
Add wells, and well/substrate connections as
described in lecture.
- [100 pts] Read Section 11.4 and design an 8x8 array multiplier (two
8-bit inputs x and y with a 16-bit output, product)
using the structure shown in Figure 11.30. Do not design a Half Adder
(HA) and use your Full Adder (FA) instead. When the figure shows a HA,
simply use a FA and connect one of the inputs to zero (50 pts)
Simulate the mult88 cell in irsim in one simulation with the following
input combinations and clearly show the inputs and correct outputs
product in an irsim output listing or waveform (40 pts). State how many
tests are correct (10 pts).
x = 00000000, y = 00000000
x = 00001111, y = 00000000
x = 00000000, y = 00001111
x = 11111111, y = 00000001
x = 00000001, y = 11111111
x = 00001010, y = 00010100
x = 01010101, y = 01010101
x = 11111111, y = 11111111
Add wells, and well/substrate connections as
described in lecture.
- [3 x 10 pts] Find the Req for the following 0.25 um transistors.
a. PMOS W = 4 lambda, L = 2 lambda, Vdd = 2.5 V
b. Two NMOS W = 8 lambda, L = 2 lambda, Vdd = 1.5 V devices in parallel
c. PMOS W = 15 lambda, L = 2 lambda, Vdd = 1.75 V (estimate it using a
reasonable method)
- [20 pts] All transistors in a 0.25um CMOS 2-input NOR gate are 10
lambda wide and 2 lambda long. Calculate the input capacitance of all
inputs if Cox = 6 fF/um^2
- [45 pts] The following gates contain PMOS transistors that are
2 times as wide as their NMOS transistors. NMOS transistors have
source/drain dimensions of LS = LD = 1 µm and W = 3 µm, where LS and LD
are the full source/drain length. For each, [5 pts] draw a schematic and
[10 pts] write an expression for the total junction capacitance on each
gate's output in terms of Cj and Cjsw
a. Inverter
b. 2-input NOR gate
c. 3-input NAND gate
- [45 pts] The heart of the original Apple iPad is the Apple A4 chip which
operates at 1.0 GHz and is believed to utilize ARM Cortex-A8 CPUs.
The chip is believed to have been built with Samsung 45nm technology.
Let's assume it dissipates 5 watts using a 1.0 V power supply.
a. [10 pts] If a prototype made in 65 nm is available, what speed and
power consumption will the chip likely have assuming constant-field
scaling?
b. [15 pts] If the supply voltage on the 65 nm part were scaled to 0.7 V,
what will the power consumption and speed be then?
c. [10+10 pts] i) What supply voltage should be used by the 45 nm part to set
the power consumption of 2.5 Watts? ii) At what speed would the processor
then operate?
- [30 pts] Draw a simplified circuit diagram of a clock network which
clocks 5 functional units in a processor: adder, subtractor, multiplier,
divider, square root. Each functional unit contains 32 flip-flops and
must be designed so that its clock can be shut off to save power. The
maximum fanout anywhere in the system is 4. The diagram should not show
all parts of the clock system, but must include enough detail so that the
structure and topology is clear.