EEC 116 - Final Project

This project consists of the design and layout of a chip which inputs a serial stream of 32 bits and outputs the bits in the form of 8 4-bit words. So the design can be scalable to handle very large bit streams, the internal memory is built with an SRAM memory array—which has 8 words of 4-bits each in this design.

Although the chip functions on a continuous 32-bit stream of bits, we can also think of the 32-bits as being eight 4-bits 2's complement numbers. The first four bits to enter the chip are output as the first 4-bit word, the next four bits as the second 4-bit word, etc. Within each 4-bit group however, you may consider that the first bit to enter the chip is the LSB (as shown in the waveform below), or the MSB--both are fine.

In a similar manner to a critical core function of a CAVLC entropy coder* in the H.264 video compression standard, your chip must count the number of 4-bit words values that are (+1, 0, -1) and output the 4-bit value as oneszeros. It must also calculate and output zeros which is the number of 4-bit values equal to zero.

All work must be done by groups composed of 2 members each. Projects by 1 person are not possible.

SRAM memory (sram.mag)

Processor (core.mag)

Chip (chip.mag)

Top-level test environment (top.mag)

Other requirements

Basic operation

  1. Clock the chip at least two cycles with reset=1 to reset necessary circuitry.
  2. 32 data bits are clocked into the chip.

  3. The chip is clocked approximately 10 more cycles for the processor to output zeros, oneszeros, and the 8 4-bit words.

Functional testing

Measuring the maximum clock rate (minimum clock period or longest logic path delay)