EEC 116 - Final Project

This project requires the design and layout of a chip which contains a high-speed digital low-pass filter. Filters are one of the most common blocks found in digital signal processors, which are increasingly popular in many electronic systems.

All work must be done by groups comprised of 2 members each. Groups of 1 person are not possible due to requirements for project classes.

Digital filter

The filter is a 5-tap or 5-coefficient finite impulse response (FIR) filter and has a saturator at its output. It processes one sample every clock cycle enabling very high data throghputs. The plot below shows the magnitude frequency response of an example 7-tap filter (with a phase plot below it). The values of the coefficients determine the specifications and type of the filter (e.g. low-pass, high-pass, etc.).

Filter architecture

The filter consists of three major components: 1) multipliers, 2) adders, and 3) registers made up of flip-flops. Use the multiplier from your Hwk as a starting point and revise it at least once to improve its area and speed.

The adders must be built with a simple ripple-carry adder structure made up of a chain of full adders. The multipliers must be built using the structure shown in Figure 11-30 in the textbook. You may use Full Adders or Half Adders for the "HA" blocks.

The filter is followed by a saturator which saturates or clips the output to be no greater than a certain level. Saturation is a common method to reduce the magnitude and word-width of signals and in some sense is complimentary to rounding.

The 5 coefficients of the filter and the saturation level are programmable.




Saturator architecture

The purpose of the saturator is to clamp or saturate the filter's output to a configurable maximum value--so it fits into a limited-width output word. A table describing its operation is below. You may build the saturator using any logic you like. The notation below is verilog-compatible. For example, abc[15:0] means the 16 signals from abc[15] to abc[0]. Underscore characters are inserted for readability only; 00_1111 is the same as the six digits 001111. Curly braces concatenate signals; {000, abc[5]} is a 4-bit signal. 

  config_sat[1:0]           sat_in[17:0]         |   sat_out[15:0]
  -----------------------------------------------+-------------------
  sat_out saturated to 16 bits                   |
      00         sat_in ≤ 00_1111_1111_1111_1111 |         sat_in[15:0]
      00         sat_in > 00_1111_1111_1111_1111 |  1111_1111_1111_1111
                                                 |
  sat_out saturated to 14 bits                   |
      01         sat_in ≤ 00_0011_1111_1111_1111 | {   00, sat_in[13:0]}
      01         sat_in > 00_0011_1111_1111_1111 |  0011_1111_1111_1111
                                                 |
  sat_out saturated to 12 bits                   |
      10         sat_in ≤ 00_0000_1111_1111_1111 | { 0000, sat_in[11:0]}
      10         sat_in > 00_0000_1111_1111_1111 |  0000_1111_1111_1111
                                                 |
  sat_out saturated to 10 bits                   |
      11         sat_in ≤ 00_0000_0011_1111_1111 | {000000, sat_in[9:0]}
      11         sat_in > 00_0000_0011_1111_1111 |  0000_0011_1111_1111

Chip structure

The diagram below shows the hierarchy of the core, clock driver, power rings, and I/O pads.

The diagram below shows the hierarchy of the chip and the test environment in top.mag

Chip pads

Pads. Design three types of pads:
  1. Power/ground--Use three VddCore and three GndCore pads for internal circuit power. Plus, add one VddIo and one GndIo for every four output pads, and one of each for every six input pads.
  2. Input into chip--include two inverter buffers.
  3. Output out of chip--include sufficient buffering to drive the output pad with a fanout no larger than 8 at any point in the inverter chain. The NMOS and PMOS of the final inverter must be separated by at least 100 λ, and must be almost entirely surrounded by appropriate-type guard rings.
    Assume pad and load capacitance is 10 pF. This is approximately equivalent to the input capacitance of 2000 near-minimum-sized inverters (10 λ PMOS, 5 λ NMOS). Copy the cell ninepF.mag to your directory and attach it to every output pad in a top level test cell (called top.mag), not in the same cell as your chip. It's large, but will make irsim timing simulations much more accurate.
Place the pads in a single ring around the edge of your chip. Power input and output buffers with VddIo and GndIo.

The I/O circuits are in a reasonably small space between the pads and power rings.

Design your pads with a 50 µm x 50 µm bonding area (paint with paint glass in magic), a 60 µm x 60 µm pad comprised of all 6 metal layers, and with a 80 µm pitch (center-to-center distance).

Power rings and power grid

Clock tree

Other requirements

Functional testing

Measuring the maximum speed

Measure the maximum speed of your design by: Remember that the minimum stepsize without pending events is the same as the minimum cycle time. The irsim clock cycle time is twice the stepsize (one stepsize is while clock is high, one while it is low). 
                     _____       _____
      clock    _____|     |_____|
      during
      test          |     |     |
                 -->|     |     |<-- irsim cycle time
                 -->|     |<-- stepsize (minimum cycle time when no pending events)
                     __    __    __
      clock    _____|  |__|  |__|  |__
      at max
      frequency
For example, if the shortest stepsize without pending events is 0.9 ns, the irsim simulation has a clock cycle time of 1.8 ns. The circuit can run at a maximum frequency of 1/0.9 ns = 1.1 GHz.

Points

Total: 350 pts + 0-150 performance pts

Fill out and submit this Summary Sheet.

Additional tasks for the group of 3 Misc.


Updates: 
2010/11/19         Written