EEC 116 - Homework 6
The purpose of this homework is to design and simulate a single
tile-able building block filter "slice" that will be used for
the final project.
You may submit a single design with your final project partner or
your own individual design.
Filter slice cell slice.mag
Design and layout a single tile-able filter slice as shown on the
final-project web page. It need not be optimized for area or speed but
must be complete.
Run the following test sequences in irsim on your single processor.
The underscore character "_" is used only to separate digits into more
easily-readable groups and does not affect the data values.
- Adder test. coefficient=0000_0000
[configure appropriately]
adder_input=00_0000_0000_0000_0000, in_data=0000_0000 # flush out
adder_input=00_0000_0000_0000_0000, in_data=0000_0000
adder_input=00_0000_0000_0000_0001, in_data=0000_0000 # begin
adder_input=00_0000_0000_0001_0000, in_data=0000_0000
adder_input=00_0000_0001_0000_0000, in_data=0000_0000
adder_input=00_0001_0000_0000_0000, in_data=0000_0000
adder_input=11_1111_1111_1111_1111, in_data=0000_0000
- Simple multiplier test. coefficient=0000_0001
[configure appropriately]
adder_input=00_0000_0000_0000_0000, in_data=0000_0000 # flush out
adder_input=00_0000_0000_0000_0000, in_data=0000_0000
adder_input=00_0000_0000_0000_0000, in_data=0000_0001 # begin
adder_input=00_0000_0000_0000_0000, in_data=0000_0010
adder_input=00_0000_0000_0000_0000, in_data=0000_0100
adder_input=00_0000_0000_0000_0000, in_data=0000_1000
adder_input=00_0000_0000_0000_0000, in_data=1000_0000
adder_input=00_0000_0000_0000_0000, in_data=1111_1111
- Full test. coefficient=1111_1111
[configure appropriately]
adder_input=00_0000_0000_0000_0000, in_data=0000_0000 # flush out
adder_input=00_0000_0000_0000_0000, in_data=0000_0000
adder_input=00_0000_0000_0000_0000, in_data=0000_0001 # begin
adder_input=00_0000_0000_0000_0000, in_data=0000_0010
adder_input=00_0000_0000_0000_0000, in_data=0000_0100
adder_input=00_0000_0000_0000_0000, in_data=0000_1000
adder_input=00_0000_0000_0000_0000, in_data=1000_0000
adder_input=00_0000_0000_0000_0000, in_data=1111_1111 # 00_1111_1110_0000_0001
adder_input=11_0000_0001_1111_1110, in_data=1111_1111 # 11_1111_1111_1111_1111
[200 pts] Points:
- Approximately-scale block-level diagram of a filter slice showing:
- [15 pts] boundaries of all major sub-blocks
inside the filter slice (e.g., show boundary of the multiplier)
- [15 pts] locations of all I/O signals
of the filter slice
- [45 pts] slice.mag layout checkoff during lab
- Irsim simulations of all input and output signals checkoff during lab
- [25 pts] Test 1.
- [50 pts] Test 2.
- [50 pts] Test 3.
Other requirements and tips
- Same as for the final project.
Updates:
2012/11/19 Posted
2012/12/05 Added clarification about block diagram