EEC 116 - Homework 6

125 total points.

Bring your paper submission to lab and include a statement for problem #2 saying how many of the tests run correctly.

For problems #1 – #2, you may submit a single design with your final project partner or your own individual design.

  1. [25 pts] Design and layout an 8-bit subtractor as described on the final-project web page. It need not be optimized for area or speed but must be complete.

    Show your layout to your TA during lab checkoff.

  2. [50 pts] Extract layout from magic and demonstrate the following test in irsim to your TA.

    Display the following signals (either by text or waveforms): in, saved_max, MSB_of_diff, diff.

    in=00000000, saved_max=00000000   # 0 - 0

    in=00000001, saved_max=00000001   # 1 - 1
    in=00000010, saved_max=00000001   # 2 - 1
    in=00000100, saved_max=00000001   # 4 - 1
    in=00001000, saved_max=00000001   # 8 - 1
    in=00010000, saved_max=00000001   # 16 - 1
    in=00100000, saved_max=00000001   # 32 - 1
    in=01000000, saved_max=00000001   # 64 - 1
    in=01111111, saved_max=00000001   # 127 - 1

    in=01111111, saved_max=00001111   # 127 - 15
    in=01111111, saved_max=00111111   # 127 - 63
    in=01111111, saved_max=01101111   # 127 - 111

    in=00000000, saved_max=00000001   # 0 - 1
    in=00000000, saved_max=01111111   # 0 - 127
    in=01000000, saved_max=01000001   # 64 - 65
    in=01000000, saved_max=01111110   # 64 - 126

  3. [30 pts] The figure below shows a signal distribution network built in 0.25 μm CMOS whose features are described in Table 4.2 on page 143. All wires are 1.00 μm wide and are routed in metal1. There are loads at each of the lettered nodes in the network that are well-modeled by capacitances of the following values: A,B,C = 100 fF; D = 75 fF; E = 50 fF. All wire segments are 1mm long unless labeled otherwise. For wire resistance, assume wires are made of Aluminium and choose and state your assumptions.
                           2mm         
         source ------+-----------+----- D
                      |           |
                      |           |    
                A ----+---- B     | 3mm
                      |           |
                      |           |
                      C           E
    
    a) [10 pts] Draw the equivalent circuit and annotate the values of resistors and capacitors, using lumped R and C models for the network.

    b) [30 pts] Since the maximum delay in a digital system is the one that limits the clock frequency, find the dominant time-constants to all five lettered nodes in the network.

  4. [20 pts] An isolated metal3 wire is 1.5 mm long, 1 μm wide, and runs over a large sheet of metal2. It is driven by a CMOS driver with very fast output rise and fall times. How will the delay change for the following cases? You may give your answer in a general sense that is true for all technologies, or use 0.25 μm data from book pp. 143-145 or inside cover. Explain your reasoning for each.

    a) [4 pts] If the wire length is doubled.

    b) [4 pts] If the wire length is cut to 1/3.

    c) [4 pts] If the wire width is doubled.

    d) [4 pts] If the wire is run over open silicon substrate instead of metal2.

    e) [4 pts] If a large 10 μm wide metal4 wire is run over the wire.



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