EEC 116 - Homework 2

1. Follow the CAD Environment Setup instructions found on the 116 homepage.
2. Go through several of the magic tutorials to familiarize yourself with the tool. At a minimum, you should go through tutorials 1, 2, 4, and 6. The tutorials are very well written and will take approximately 30-60 minutes each. Also print the tutorial notes at the top of the tutorial page and reference them while you work through the tutorials.

   When a tutorial tells you to edit a magic file, copy it from the directory /pkg/cad/lib/magic/tutorial/ to your local working directory so you can edit it.

   To copy all the tutorials to your home directory, first make a folder to contain all the files, copy the files to this folder, then make the files writeable. For example:
   

   1. mkdir ~/magic
   2. cd ~/magic
   3. cp /pkg/cad/lib/magic/tutorial/tut*.mag .
   4. chmod +w tut*.mag
   You could also copy files one at a time with a command like: cp /pkg/cad/lib/magic/tutorial/tut1.mag .

We will make several small changes to the magic tutorial procedures. They are:


• Only make labels as "points" meaning small "+" shapes and never covering a larger region. This avoids some problems.
• Never use global labels! (labels ending in "!".)
• More to come...
3. Draw the schematics, stick diagrams, and layout for six circuits:
1. an inverter
2. a 2-input NAND gate
3. a 2-input NOR gate
4. a 5-input NOR gate (five NMOS transistors in parallel, five PMOS transistors in series; same general structure as 2-input NOR)
5. A single CMOS transmission gate (an NMOS in parallel with a PMOS) followed by a single inverter. Label the NMOS gate J, and include a second inverter which generates J and connect it to the PMOS gate.
6. 10 inverters chained together in series

Place labels on the following nodes:
• Vdd (power)
• Gnd (ground)
• A input (inverter); B and C inputs (2-input NAND); D and E inputs (2-input NOR); F, G, H, I, J inputs (5-input NOR); K input (CMOS transmission gate input)
L input (first inverter in 10-inverter chain)
• U, V, W, X, Y, and Z outputs respectively

All transistor gate lengths must be minimum length (which is 2 λ). There is no need to draw the nwell or pwell for this assignment. Use metal1 for Vdd, Gnd, and gate outputs and route signals in ndiff or pdiff for short distances only.
4. Turn in for each of the circuits:
   • schematic drawn on paper [2 pts each],
   • stick diagram drawn on paper [2 pts each],
   • plot of layouts printed on paper with each circuit on a half page or full page [4 pts each]. Use the Printing Designs instructions found on the 116 homepage.

2012/10/09  Posted