EEC 116 - Homework 2
The purpose of this homework is to familiarize you with the magic
layout tool and to layout some basic circuits. Do your work
Resist the temptation to look at layout on the internet or from
other sources (it will be obvious to me if you do). This is
perhaps the only assignment in your life where the quality of your
layout does not matter and only the correct connections matter.
You will learn far more and later layout guidelines will stick
in your mind much better if you do your layout (in terms of
sizing, location, orientation, routing material, etc.) in whatever way
makes the most sense to you. There will be plenty of time for
compact and regular layout in the future.
- Follow the
CAD Environment Setup instructions
found on the 116 homepage.
- Go through several of the
magic tutorials to
familiarize yourself with the tool. At a minimum, go through
tutorials 1, 2, 4, and 6 at this time. The tutorials are very
well written and will take approximately 30-60 minutes each.
Print the Tutorial Errata at the top of the tutorial page
and reference them while you work through the tutorials.
- Draw the schematics, stick diagrams, and layout for
- An inverter
- A 2-input NOR gate
- A 2-input NAND gate
- A 4-input NAND gate (four NMOS transistors in series,
four PMOS transistors in parallel; same general structure
as 2-input NAND)
- A single CMOS transmission gate (an NMOS and PMOS with
their Source and Drain connected to the other transistors'
Source and Drain) followed by a single inverter.
Label the NMOS gate M, and include
a second inverter which generates
connected to the PMOS gate.
- 9 inverters chained together in series
Place labels on the following nodes:
- Vdd (power)
- Gnd (ground)
- A input (inverter);
B and C inputs (2-input NOR);
D and E inputs (2-input NAND);
F, G, H, I inputs (4-input NAND);
J input (CMOS transmission-gate input)
K input (first inverter in 10-inverter chain)
- U, V, W, X, Y, and Z outputs respectively
All transistor gate lengths must be minimum length (which is
2 λ). There is no need to draw the nwell or pwell for
this assignment. Use metal1 for Vdd, Gnd, and gate outputs
and route signals in ndiff or pdiff for short distances only.
Turn in for each of the circuits:
- schematic drawn on paper [2 pts each],
- stick diagram drawn on paper [2 pts each],
- plot of layouts printed on paper with each circuit on
a half page or full page [4 pts each].
Use the posted Printing