EEC272: High-Performance Computer Architecture: Super-Scalar Processor Design
Prof. Vojin G. Oklobdzija
Electrical and Computer Engineering Department
University of California
List of recommended readings:
[1] C.J. Bashe et al., "The Architecture of IBM's Early Computers", IBM Journal of Research and Development, 25:5 (Sep 1981), p.363-375.
[2] G.M. Amdahl, G.A. Blauuw, F.P. Brooks, Jr, "Architecture of the IBM System/360", IBM Journal of Research and Development, 8:2 (April 1964), p. 87-101.
[3] G.A. Blaauw and F.P. Brooks, "The Structure of System/360", IBM Systems Journal, 3:2 (1964), p.119-135.
[4] A. Padegs, "System/360 and Beyond", IBM Journal of Research and Development, 25:5 (Sep 1981), p.377-390.
[5] James E. Thornton, "Parallel Operation in the Control Data 6600", AFIPS Proceedings FJCC part 2, vol 26 (1964), p.33-40.
[6] R.M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", IBM Journal, vol 11 (Jan 1967), p.25-33.
[7] D.W. Anderson et al., "The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling", IBM Journal, vol 11 (Jan 1967), p.8-24.
[8] Johnny K.F. Lee and A.J. Smith, "Branch Prediction Strategies and Branch Target Buffer Design", Computer, 17:1 (1984), p.6-22.
[9] Wen-mei W. Hwu et al., "Comparing Software and Hardware Schemes for Reducing the Cost of Branches", Proc. of the 16th International Symposium on Computer Architecture, (1989), p.224-233.
[10] A.J. Smith, "Cache Memory Design: An Evolving Art", IEEE Spectrum, (Dec 1987), p.40-44.
[11] A.J. Smith, "CPU Cache Memories", (Apr 1984), updated version of ACM Surveys, 14:3 (Sep 1982), p.473-530.
[12] A.J. Smith, "Cache Evaluation and the Impact of Workload Choice", Proc. of the 12th International Symposium on Computer Architecture, (1985), p.64-73.
[13] A.J. Smith, "Line (Block) Size Choice for CPU Cache Memories", IEEE Trans. on Computers, C-36:9 (Sep 1987), p.1063-1075.
[14] J.S. Liptay, "Structural Aspects of the System/360 Model 85, Part II: The Cache", IBM Systems Journal, 7:1 (1968), p.15-21.
[15] Peter J. Denning, "Virtual Memory", Computing Surveys, 2:3 (Sep 1970), p.153-189.
[16] Albert Chang and Mark F. Mergen, "801 Storage: Architecture and Programming", ACM Transactions on Computing Systems, 6:1 (Feb 1988), p.28-30.
[17] C.V. Ramamoorthy, "Pipeline Architecture", Computing Surveys, 9:1 (Mar 1977), p.61-101.
[18] G. F. Grohoski, "Machine Organization of the IBM RISC System/6000 Processor", IBM Journal of Research and Development, 34:1 (Jan 1990), p.37-58.
[19] Case Study: "IBM's System/360-370 Architecture", Communications of the ACM, 30:4 (Apr 1987), p.291-307.
[20] P. H. Gum, "System/370 Extended Architecture: Facilities for Virtual Machines", IBM Journal of Research and Development, 27:6 (Nov 1983), p.530-544.
[21] N. P. Jouppi, D. W. Wall, "Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines", WRL Technical Note TN-2, (Sep 1988), 23 pages.
[22] George Radin, "Research Report: The 801 Minicomputer", IBM Thomas J. Watson Research Center, (Nov 1981), 23 pages.
[23] M. E. Hopkins, "A Perspective on the 801/Reduced Instruction Set Computer", IBM Journal of Research and Development, 26:1 (1987), p.107-121.
[24] Technical Report, "System 801: Principles of Operation", IBM Journal of Research and Development, (Nov 1976), 57pages.
[25] Richard Matick, "Functional Cache Chip for Improved System Performance", IBM Journal of Research and Development, 33:1(Jan 1989), p.15-32.
[26] Richard Matick, "Memory Hierarchies and Virtual Memory Systems", IBM, p.549-643.
[27] Richard Matick, "Impact of Memory Systems on Computer Architecture and System Organization", IBM Systems Journal, 25:3/4, (1986), p.274-305.
[28] J. Beetem, M. Denneau, D. Weingarten, "The GF-11 Supercomputer", reprinted from the Proc. of the 12th International Symposium on Computer Architecture , (1985), p. 108-115.
[29] Victor Zyuban et. al., "Integrated Analysis of Power and Performance for Pipelined Microprocessors", IEEE Trans. on Computers, 53:8, (2004), p. 1004-1016.
[30] J. E. Thornton, "Design of a Computer - The Control Data 6600", Scott, Foresman and Company, (1970), 100 pages.
[31] James E. Smith, "Decoupled Access/Execute Computer Architectures", Proc. of the 9th International Symposium on Computer Architecture, (1982), p.112-119.