EEC 181A/B - Digital Systems Design Project
Spring 2024

General Course Information

Graded Work and Policies

Lab Information

Course Topics, Slides, Notes, and Handouts

Many of the early lectures will consist of a high-speed review of concepts covered in EEC 180 so your benefit will be far greater if you read the posted handouts before lecture and come with questions.

Future details are tentative.

Date Lecture Notes, Handouts, and Reading Assignments
Tue, Jan 9 Course introduction
Digital design overview
Basics of digital systems
Lecture 1 notes
 
Tue, Jan 16 Verilog overview I Basic units
Basic diagramsJAN 16 (minor notes regarding the pipelined block diagram)
HDL to hardware
Verilog 1: Overview
Verilog 2: Basics
 
Tue, Jan 23 Verilog overview II
Binary number formats
Binary coded decimal (BCD)
Binary fractional
Addition hardware
Subtraction hardware
Sign extension for 2's complement
Memories
Single-bit memory elements
Flip-flops and 9 rules of using them
Flip-flops with reset, preset, enable
Four structures in HW verilog
Lecture 3 notes
Verilog quick ref guide, S. Sutherland (skim quickly) [orig]
Verilog 3: Time and delay
Verilog 4: Common mistakes
Verilog 5: Testing
Verilog 6: Decoder example
Binary number formats
Ref: Addition/subtraction
Sign extension
Single-bit memories (FFs)
Lab 1
due Th, Jan 25
Tue, Jan 30 Memories I
Four verilog constructs
Memories
 
Tue, Feb 6 Memories II
M10K memory blocks
Control circuits
Counters
Finite state machines
M10K memories
Control Circuits and Counters
Finite State Machines
Lab 2
due Th, Feb 8, 6:00pm
Tue, Feb 13 Critical timing requirements of digital systems
Pipelines
Pipeline throughput and latency I
Critical timing requirements
Pipelining

 
Tue, Feb 20 Clocks
Multiple-frequency clocking
Saturation I
Clocks
Variable-freq clock hardware
Saturation
Lab 3
due Tue, Feb 20
Tue, Feb 27 Saturation II
VGA video interfaces
VGA sync signals
Pipeline throughput and latency II
Pipelining systems


Tue, Mar 5 System-Level design
Interfacing with unsync inputs: debouncing, edge detection
Block interfaces, timing, interconnect
Lab 5 video pixel processing overview
Steps to design systems
Interfacing input signals
Lab 4
vga_top.zip
due Tue, Mar 5
Tue, Mar 12 Design consulting Design consulting

Lab 5
DE1_D8M.v5.zip
due Th, Mar 14
Date Lecture Notes, Handouts, and Reading Assignments

Final Project Description Updated: TBD 

Wed, Mar TBD Course overview Lecture 11 notes

 
Wed, Apr TBD Group meetings Lecture 12

 
Wed, Apr TBD Group meetings, Milestone #1 checkoff Lecture 13

 
Wed, Apr TBD Group meetings Lecture 14

 
Wed, Apr TBD Group meetings Lecture 15

 
Wed, May TBD Group meetings, Milestone #2 checkoff Lecture 16

 
Wed, May TBD Group meetings Lecture 17

 
Wed, May TBD Group meetings Lecture 18

 
Wed, May TBD Group meetings Lecture 19

 
Wed, Jun TBD Group meetings Lecture 20

 
Jun TBD x:00-x:00pm
Room TBD
Group presentations
  • Group 1
  • Group 2
  • Group 3
  • Group 4
  • Group 5
 

 


EEC 181 | B. Baas | ECE Dept. | UC Davis

Changes made will generally be colored green, except basic information in tables.

Last update: March 21, 2024