This tutorial describes a method to use the 64 MB Synchronous Dynamic Random-Access Memory (SDRAM) located on the DE1-SoC board—this memory is not located inside the FPGA chip. Please note the sample project provided below works only with Quartus Prime and not with Quartus II.
The code and documentation in its original form was written by Terasic and was written specifically to buffer a single frame of pixels for a 640x480 VGA camera and display (307,200 pixels). Data is written in order and later read out in order. To read or write the data in an arbitrary order, use a buffer memory to reorder the data before/after performing the write/read with the SDRAM.
Although easy to change, the current design will overwrite old data after every 307,200 writes. The pin "WR_ENABLE" performs a write into the SDRAM while it is high. The pin "RD_ENABLE" similarly performs a read of the SDRAM while it is high.
The SDRAM is set to run at a clock frequency of 125 MHz. The design has been verified to run error-free on the DE1-SoC board with a system clock rate of 25 MHz or 50 MHz at a maximum rate of one write and one read per clock cycle. The current design does not work at one write and read transaction per cycle at a system clock rate of 125 MHz (although not yet tested or designed, we think it would work if a write and read were not performed each clock cycle, or the DRAM were modified to run at a higher clock rate—it can run up to a maximum clock frequency of 143 MHz with the CAS parameter set to 3, or up to 133 MHz with CAS set to 2).
sdram.module.user.documentation.pdf, provides an overview of the functionality and use of the SDRAM memory.
sdram.zip, contains the modified verilog source code
sdram.data.sheet.ISSI.pdf is the primary datasheet from the vendor ISSI.
2022/04/22 Added ISSI datasheet, minor additions and edits 2022/04/21 Written Written by Ziyuan Dong and Bevan Baas