EEC180 Tutorial: FPGA Maximum Operating Frequency

Quartus' Timing Analysis

As part of the compilation process, Quartus performs a timing analysis on the post place-and-routed design. You can view the results of the timing analysis by viewing Quartus' Compilation Report and expanding the menu under "TimeQuest Timing Analyzer". Quartus provides several timing reports at different operating conditions. For EEC 180, we are normally interested in only the most pessimistic (slowest) model which is the "Slow 1200mV 85C Model."

Expand the menu under this heading and click on the "Fmax Summary" item. The reported clock frequency is the fastest that the current design can be clocked without violating the setup time of any flip flops.

Requirements for Proper Timing Analysis

For the analysis to function, the circuit being examined must contain registers and a valid clock which clocks the registers. If these are not implemented, the tool will return: "No paths to report".

A Circuit's Maximum Operating Frequency

Although the clock frequency mentioned in Section 1 is reported under the name "Fmax Summary", the name is a little mis-leading because this number is not the absolute fastest the circuit can be clocked. To understand this, open the "SDC" file for this project ("SDC" stands for "Synopsys Design Constraints"). You should see the command:

create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50]

in the SDC file. This informs Quartus that the input MAX10_CLK_50 (the crystal oscillator clock on the DE10-Lite) will be used as a clock and that the frequency of this clock is 50 MHz. Since this is the clock that is used in the design, Quartus needs to ensure only that its synthesized circuit can run at least 50 MHz. Once this goal is achieved, Quartus will focus on other optimization goals such as using fewer chip resources or reducing power dissipation.

In Figure 1, four example waveforms are shown below a clock signal with blue hash areas indicating time periods when the signals are propagating through logic between clocked registers (positive-edge-triggered flip flops in this case). The signal config requires almost the entire clock period—implying the circuit is being clocked very close to its maximum clock frequency.


Figure 1. Example waveforms showing four data signals that require almost a complete clock cycle to resolve.

Achieving the Maximum Operating Frequency

Changing the clock speed in the SDC file does not increase the frequency of the crystal oscillator on the DE10-Lite board—it only changes the frequency target given to Quartus.

By increasing the specified clock frequency in the SDC file, Quartus can be forced to continue optimizing the circuit for increased speed until the tools simply cannot optimize and place the circuit on the FPGA in such a way that the target clock frequency is achieved.

Except under very unusual circumstances, if a digital design runs at a certain frequency, it will also run at any lower frequency, so increasing the frequency of the clock will not hurt the functionality of the final design. The converse is not true.

To achieve the maximum operating clock frequency, increase the constrained clock frequency (i.e. the "50 MHz") in the design's SDC file until Quartus cannot meet timing constraints. You will know when this happens because the folder "Slow 1200mV 85C Model" in the Compilation Report will be highlighted in red. The highest successful frequency is the maximum operating frequency for your design.

2018/05/05  Minor edits (BB)
2019/06/11  Minor clarifications in Section 4 (BB)
Written by Mark Hildebrand and Bevan Baas