A visual diagram showing the resources used by a particular design can be viewed with Chip Planner which is invoked by clicking the Tools menu and then selecting Chip Planner.
Figure 1. Example chip planner resource map diagram shown by Quartus. Click image to show in a larger resolution.
View a summary report by clicking
View Report
in the left pane. Then click the first item in the center window called:
Flow Summary
which will show the summary in the right pane.
The most interesting values include:
- Logic utilization
- Total registers
- Total block memory bits
- Total DSP blocks
- Total PLLs
Figure 2. Example summary resource information shown by Quartus. Click image to show in a larger resolution.
For the detailed resource information, click
Resource Usage Summary
in the center pane to show the detailed resource information in the right pane.
Many details of the key parameters shown in the summary view can be seen here and in addition, some interesting parameters visible here include:
- Difficulty packing design
- Breakdowns of the number of inputs of functions built by ALUT logic
- Hard processor system usages
- Global signals
- M10K blocks
- MLAB blocks
- Total MLAB memory bits
- Total block memory bits (I believe this is M10K)
- Total DSP blocks
- Global clocks
Figure 3. Example detailed resource information shown by Quartus, view of the top section of the right pane's information. Click image to show in a larger resolution.
Figure 4. Example detailed resource information shown by Quartus, view of a lower section of the right pane's information. Click image to show in a larger resolution.