Tutorial: Creating, compiling, and downloading a design into the FPGA board

1. Run SystemBuilder

   Create a new folder/directory for your project. Use SystemBuilder to create a new project, give it a title, and save it in this project directory. Include necessary circuits and interfaces to on-board components such as the: Clock, SW Switches, KEY Buttons, LEDs, HEX displays, etc. Generate the project and close SystemBuilder.

2. The top-level verilog module

   Enter your verilog design code into the top-level module.

   The header of the top-level module should include the following clock-input definitions:

       //////////// CLOCK //////////
       input ADC_CLK_10,
       input MAX10_CLK1_50,
       input MAX10_CLK2_50,
   

   Either of the latter two clocks may be used for the standard 50 MHz clock. According to the manual, the two clocks are generated by the same off-chip fixed-frequency clock generator, but come in on different pins on the FPGA so they should probably not be mixed without care. (Note: they come out of different pins from the off chip generator.)

   To make your code easier to read (assuming you need a clock in your design), it is advisable to add a wire declaration statement like the following that will allow you to use the wire "clock" for your clock signal.

       wire clock;
       assign clock = MAX10_CLK1_50;
   

3. Add verilog modules to the Quartus project

   Open the project in Quartus by double-clicking on the *.qpf file (which was made by SystemBuilder).

   Add all *.v files from the hdl/ directory.

   • In the Project Navigator pane of Quartus, select "Files" in the pull-down menu. The first line in the pane will change to "Files".

   • Right click "Files" and choose the "Add/Remove files in project..." selection.

   • In the popup window, click the three dots "..." at the end of the row that begins with "File name:". Navigate to the hdl/ directory by going up a level and then entering the hdl/ directory.

   • Select all necessary *.v files and then click "Open" to add them. Click "ok".

   • In some cases selecting a file and then clicking "Open" does not add the file to the list as it should. In this case, simply manually add the relative path of the file (e.g., "../hdl/abc.v") in the box next to the "Add" button, then click "Add".

   Do not add any testbench files to the project since testbench files are never used in hardware designs and only hardware is handled by Quartus.

4. Add any other necessary modules to the Quartus Project

   Add any other necessary verilog modules such as converters for displays, accelerometers, etc.

5. Optional: View or change the default (50 MHz) target maximum operating clock frequency

   Open the "SDC" file for this project ("SDC" stands for "Synopsys Design Constraints"). You should see the command:

       create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50]

   in the SDC file. This informs Quartus that the input MAX10_CLK_50 (the crystal oscillator clock on the DE10-Lite) is to be used as the clock and that the frequency of this clock is 50.0 MHz. Since this is the clock that is used in the design, Quartus just has to ensure that its synthesized circuit can run at or faster than 50 MHz. Once this goal is achieved, Quartus can focus on other optimization goals such as using fewer CLBs or lowering power.

   By increasing the specified clock frequency in the SDC file, Quartus is forced to focus more on optimizing the circuit for speed until the tools simply cannot optimize and place the circuit on the FPGA in such a way that the target clock frequency is achieved.

   NOTE: Increasing the clock frequency in the SDC file does not actually increase the frequency of the crystal oscillator on the board. The only change is that Quartus is given a faster timing target. In general, if a design is able to run at a certain frequency (e.g., 60 MHz), it will also run at a lower frequency (e.g., 50 MHz), so increasing the target clock frequency will not hurt the functionality of the final design. The converse is not true. If you really want to increase the clock frequency on the FPGA, you will have to configure and instantiate a PLL in your design. See the tutorial: Instantiating and using a PLL on the DE10-LITE board

6. Compile the design

   Navigate over to the "Tasks" pane in Quartus. By default, this window will be located around the left middle of the screen. Right click on "Compile Design" and select Start. This will run the entire compilation process. (If desired, a specific substep of compilation can be performed by right clicking on the desired operation and selecting "Start".)

   Make sure you deal with any errors that occur during the compilation process. These can be seen either in the "Processing" pane located by default at the bottom of the screen, or under "Flow Messages" in the Compilation Report. Error messages can be filtered by clicking on the red and white "X".

   Every time you compile a design, look at the warnings generated. These are also found in the Flow Messages and can be filtered using the yellow triangle with a white "!". Some warnings such as "Number of processors has not been specified ..." can be safely ignored. However, other warnings (such as "inferred latches" or pins not driving logic) can indicate a logical flaw in the HDL that must be addressed.

7. View the timing results

   As part of the compilation process, Quartus performs a timing analysis on the post placed-and-routed design. You can view the results of the timing analysis by going to Quartus' Compilation Report and expanding the menu under "TimeQuest Timing Analyzer".

   Quartus provides several timing reports at different operating conditions. Unless you are told otherwise, for 180 you should use the most pessimistic (slowest) model which is the "Slow 1200mV 85C Model". Expand the menu under this heading and click on the "Fmax Summary" item. The reported clock frequency is the fastest that the current design can be clocked without violating the setup-time of any flip flops.

8. Download the project into the DE10-Lite board

   Open the Programmer by selecting Tools > Programmer.

   If the field next to "Hardware Setup" reads "No Hardware", click the Hardware Setup button and switch the selected hardware to the USB-Blaster.

   JTAG chain (picture on the bottom of the programmer pop out) has two devices. If the device does not show up, use "Select Devices" to add the device. Then remove the auto-added "{project_name}.sof" file and use "Add File" to add the "{project_name}.sof" file. The .sof should be on the tail of the JTAG chain.

   Click Start to download the design to the board. After a brief pause, you should see the message 100% (Successful) and your design will now be running on the DE10-Lite board.

2020/05/17  Add the "The top-level verilog module" section and re-wrote and re-organized text (BB)
2020/04/20  Re-wrote Section 7 plus various edits (BB)
2018/05/05  Minor edits (BB)
Written by Mark Hildebrand and Bevan Baas