pic

EEC 180 - Digital Systems II
Spring 2021

General Course Information

Graded Work and Policies

Lab Information

Course Topics, Slides, Notes, and Handouts

Future details are tentative.

Date Reading Lecture Notes, Handouts, and Reading
Tue, Mar 30 Chapter 1, 2
Chapter 3 if needed
Course introduction
Digital design overview
Basics of digital systems
Lecture 1 slides
Lecture 1 notes
Th, Apr 1 Chapter 6 if needed
Chapter 7 (Verilog)
Appendix A
Basic units
Basic diagrams
Design flow HDL to HW
Verilog Overview
Lecture 2 notes
Basic units
Seven basic diagrams
Chip design methodologies
HDL to HW
Tue, Apr 6   Verilog Language basics I

Lecture 3 notes
Verilog 1: Overview
Verilog 2: Basics
Th, Apr 8 Chapter 8 (Comb. Blocks) Verilog Language basics II
Verilog wire, assign
Verilog reg, always block
Lecture 4 notes
Example: NAND2
Verilog quick ref guide, S. Sutherland (skim quickly) [orig]
Tue, Apr 13 Chapter 9 (Comb. Examples) Verilog Language basics III
Verilog Time and delay
Verilog Common mistakes
Verilog Testing I
Lecture 5 notes
Verilog 3: Time and delay
Verilog 4: Common mistakes
Verilog 5: Testing
Th, Apr 15 Chapter 10 (Binary #s, Arith)
Verilog Testing II
Binary number formats
Binary coded decimal (BCD)
Binary fractional
Lecture 6 notes
Binary number formatsAPR 15
Tue, Apr 20 Chapter 11 (Fixed/Float Pt)
Addition
Subtraction
Design example: Decoders
Sign extension for 2's complement
Memories
Lecture 7 notes
Addition/subtraction
Verilog 6: Decoder example
Sign extension
FFs and registers
Th, Apr 22 Chapter 13 (Arith. examples)
Quiz — (zoom instructions)
Single-bit memory elements
Flip-flops and 9 rules of using them
Lecture 8 notes
Tue, Apr 27   Flip-flops with reset, preset, enable
Four structures in HW verilog
Control circuits
Counters
Lecture 9 notes
Four verilog constructs
Control Circuits and Counters
Th, Apr 29

Chapter 14 (Seq. Logic)
Finite state machines
Lecture 10 notes
Finite State MachinesAPR 29
Example FSM circuit diagram
Counter example with four views (view in slide show mode)
Tue, May 4 Chapter 16 (Datapath Seq. Logic)
 
FSM design example
Clocks
Critical timing requirements of digital systems
Lecture 11 notes
Clocks
Critical timing requirements
Th, May 6
Chapter 17 (Factoring FSMs)
Chapter 19 (Seq. Examples)
Interfacing with unsync inputs: debouncing, edge detection
Lecture 12 notes
Interfacing input signals
Tue, May 11 Chapter 15 (Timing)
 
Multiple/variable freq clock hardware
Lecture 13 notes
Variable-freq clock hardware
Midterm overview
Th, May 13   Midterm — (zoom instructions)

Tue, May 18 Chapter 23 (Pipelines)
 
Pipelines
Pipeline throughput and latency
Pipelining systems
Lecture 14 notes
Pipelining
Th, May 20 Chapter 25 (Memory Sys)
 
Memories I
Lecture 15 notes
Total grade class histogram as of May 20
Memories
Tue, May 25   Memories II
Bit-slicing memory arrays
Banking memory arrays
Lecture 16 notes
Th, May 27 Chapter 21 (Sys-Level Design)
 
Memory timing
M9K memory blocks
Lecture 17 notes
M9K memories
Tue, Jun 1 Chapter 22 (Interface & Sys-Level Timing)
Chapter 24 (Interconnect)
System-Level design
Block interfaces, timing, interconnect
Lecture 18 notes
Steps to design systems
Th, Jun 3 Field-Programmable Gate Arrays (FPGAs)
Estimating circuit complexity
Data word growth
Binary multiplication
Arithmetic: Rounding
Arithmetic: Saturation
Lecture 19 notes
FPGA tutorial, 7 pages
FPGA vendors and major internal components
Estimating chip area
MultipliersJUN 3
Rounding
Ref: Saturation
Fri, June 4
3:30pm–5:30pm
Final Exam — (zoom instructions)

Saturday, June 5 Office hour 9–11am, Satyabrata Sarangi
Office hour 11–1pm, Tony Tsoi
Office hour 1–3pm, Harichandana Chitturi
Sunday, June 6 Office hour 9–11am, Ziyuan Dong
Office hour 11–1pm, Shifu Wu
Monday, June 7 Final chance for Lab 7 checkoffs.
To reserve a time slot, click here: https://forms.gle/YkWDTtmcK8agvu7J6
12–2pm Tue, June 8
12–1:30pm Wed, June 9
11–1pm Thur, June 10
Return DE10-Lite FPGA Boards
Bring to Kemper Courtyard at these times, or ship it

Assignments

Future details are tentative.

Week Prelab due and
work in Lab
Checkoffs and
uploads due
Hwk due
Friday, 5pm
Homework problems
(Problems are tentative until approximately the Thurs 8 days before the due date, depending on material covered in lecture)
Mar 29 – Apr 2
No lab - - -

Apr 5 – Apr 9 Lab 1
Cover sheet not needed
- - -

Apr 12 – Apr 16

Lab 2
Lab 1 1
2.3, 2.10, 2.17
7.1, 7.7 (assume true=1), 7.24 (no need to test)
8.4, 8.15, 8.18, repeat 8.18 writing verilog not using building blocks
Apr 19 – Apr 23

Lab 3APR 21

Lab 2 -
-
Apr 26 – Apr 30

Lab 4

Lab 3
2
9.1, 9.14
10.14, 10.15, 10.23 (circuit diagram), 10.25–10.28 (sign mag and 2's comp only), 10.29 (use A + (-B), 10.40
11.3, 11.11
May 3 – May 8
Lab 5
Lab 4

-
-
May 10 – May 14 No new lab

- 3
13.14
14.6, 14.7, 14.8, 14.18, 14.19
15.1, 15.8, 15.10
16.17–16.19 (no need to simulate)
May 17 – May 21 Lab 6MAY 18
Video demo
Lab 5
-
-
May 24 – May 28 Lab 7JUN 2
Video demo

Lab 6
4
19.1, 19.6
25.1, 25.2 using primitive in "Memory" Handout instead
May 31 – Jun 4

- -
-
-
Mon June 7, 4pm

- Lab 7
 
 

Videos of previous labs



EEC 180 | B. Baas | ECE Dept. | UC Davis

Changes made will generally be colored green, except basic information in tables.

Last update: January 17, 2024