Tips for building and debugging your circuits

Tips for Building Circuits

1. The fastest way to get a design working is to spend lots of time thinking and debugging mentally and "testing" with pencil and paper. Draw waveforms, think of test cases, and think through various modes with paper and pencil. Make sure you know exactly how each part works and be fairly confident of what is right even before you enter the design into the computer, much less load it onto the FPGA board. I guarantee your understanding will be far greater, you will have a much greater chance of it working, and assuming it works, you will be done much sooner if you do this.

2. If possible, it is often helpful to check circuit functionality as you build. Build a small sub-circuit, then test its result before moving on to another sub-circuit.

3. The later labs require a lot of time especially for debugging—plan for it!

Tips for Debugging Circuits

1. Often adding intermediate results (i.e., additional LEDs or indicators), helps to isolate problems especially in large circuits.

2. When a circuit fails in simulation, always always focus on the first error you can identify. Never spend time on later failures until the first one is fixed.

3. Starting with the inputs, verify all inputs to a gate then the output. If the inputs look OK, but the output is not correct, the problem has been isolated to that gate.

4. Continue moving towards the output and try to isolate problems.

5. If nothing is helping to isolate the problem, remove circuits from your design until something starts working.

Common Errors

1. expecting an identifier (Quartus)
   unexpected INTEGER NUMBER (Modelsim)

   Verilog names must begin with a letter or underscore (a-z, A-Z, _). The name may contain alphabetic characters, numerals, underscore characters, or dollar signs (a-z, A-Z, 0-9, _, $). Verify your module names, wires, and regs follow these requirements.

2. error loading design (Modelsim)

   Verify the .v file has the same name as the name of the top-level module in the file.

3. error loading design or undefined project (Modelsim)

   Verify you followed the recommended directory organization shown in another 180 tutorial.

4. Can not find "console output"

   Check the transcript window (view → check Transcript).

2020/05/02  Removed and added several points (BB)
2018/05/05  Minor updates (BB)
2019/03/14  Minor updates (BB)
Written by Bevan Baas