EEC180 Tutorial: Using the accelerometer on the DE10-LITE board

EEC180, Digital Systems II


  1. Overview

    2. The DE10-Lite FPGA board contains a 5-axis ADXL345 accelerometer chip (commonly referred to as the "G-Sensor") which may be used to measure the orientation of the board. This tutorial describes how to read x-axis and y-axis data from the accelerometer 50 times per second.

    Check the Accelerometer option when you first build your project using SystemBuilder.

    The interface is a little complex however the necessary code and instructions are provided in the following .zip file:

    Copy the following files to the hdl/ folder in your project folder:
        hdl/accel.v
        hdl/spi_control.v
        hdl/spi_serdes.v

    As a reference, some testbench code is available in the "test/" directory of accelerometer.zip if needed for in-depth debugging but it is not needed for normal usage.

  2. Description of Modules

    3. Details on how to use "spi_control" are given below.

    1. spi_control.v

      This is the higher-level module for controlling interactions between the "Primary" FPGA and "Secondary" accelerometer. This module initializes the accelerometer chip on the DE10-Lite PCB and then periodically samples the x- and y-axes of the chip. To use this module, carefully read the following summary of the parameters and ports. In particular, note the special requirements for providing 3 clock signals to the module. Details for generating these three clocks are given at the end of this tutorial.

      Parameters

      • "SPI_CLK_FREQ" - The frequency (Hz) of the clock used to communicate with the SPI secondary. This is the clock frequency that most of the internal logic of "spi_control" and "spi_serdes" will use. This has been tested at only 2 MHz. Unless you are told otherwise, do not change this value.

      • "UPDATE_FREQ" - The frequency (Hz) at which to sample new values from the G-Sensor. This has been tested at only a value of 50 Hz. Unless you are told otherwise, do not change this value.

      Ports

      • "reset_n" - When "0", reset all internal logic.

      • "clk" - The clock of the logic using this module. This clock is provided to ensure that "data_update" is high for only one clock cycle of the instantiating module. This signal has been tested at only 25 MHz and 50 MHz.

      • "spi_clk" - Clock used for driving SPI logic internally. **NOTE: This clock must be in phase with "clk". If it is not, timing closure might not be achieved.**

      • "spi_clk_out" - Clock used for driving SPI logic externally. **NOTE: Must be the same frequency as "spi_clk" but 270 degrees ahead.**

      • "data_update" - Control flow signal, high for one clock cycle when new values for "data_x" and "data_y" are valid and available. When this signal is not "1'b1", the validity of "data_x" and "data_y" is not guaranteed. These ports must be sampled as soon as "data_update == 1'b1".

      • "data_x" - 16 bit 2's complement signed value for the x-axis of the G-Sensor (tipping the board left and right when the 7-segment displays are facing you). It is guaranteed valid only when "data_update == 1'b1"

      • "data_y" - 16 bit 2's complement signed value for the y-axis of the G-Sensor (tipping the board forward and back when the 7-segment displays are facing you). It is guaranteed valid only when "data_update == 1'b1"

      • "SPI_CSN" - Chip select for SPI protocol. Route directly to the port with the same name in the top level module.

      • "SPI_CLK" - Clock for SPI protocol. Route directly to the port with the same name in the top level module.

      • "SPI_SDI" - Clock from SPI primary to secondary. Route directly to the port with the same name in the top level module.

      • "SPI_SDO" - Data wire from SPI secondary to primary. Route directly to the port with the same name in the top level module.

    2. spi_serdes.v

      This module contains a SERializer/DESerializer (serdes) for the 4-wire SPI protocol used for communication between the "Primary" FPGA and "Secondary" accelerometer. Your design will interface with only the spi_control.v module, which instantiates and interacts with the spi_serdes.v module. This module is somewhat specialized for the interchange behavior between primary and secondary blocks and does not support burst reads/writes.

  3. Configuring the Clocks with a Phase-Locked Loop (PLL)

    4. The three required clocks "clk", "spi_clk", and "spi_clk_out" may all be generated using a single PLL IP core. Refer to the PLL tutorial for instructions on how to instantiate a PLL.

    When instantiating, configure the clocks "c0", "c1" and "c2" with the following values: 

    * c0 - Freq: 25 MHz, Phase: 0 
* c1 - Freq: 2 MHz, Phase: 0 
* c2 - Freq: 2 MHz, Phase 270

    Your own module should use clock c0 as its clock.

    Connect these output clocks to the following input ports of the "spi_control" module: 

    * c0 → clk
* c1 → spi_clk
* c2 → spi_clk_out

  4. Magnitude of the Outputs

    5. Although the outputs of the accelerometer are 16-bit 2's complement, values are typically in the approximate range [–260, +260] but they have been observed up to [–500, +500].

  5. Timing of the Outputs

    6. For all practical purposes, new accelerometer output values can arrive at any time however are synchronized to the main clock (25 MHz or 50 MHz).

    Therefore, applications that require new accelerometer output values at certain times will need to buffer the accelerometer's outputs. The simplest buffer would be a single 16-bit register that is written when the accelerometer's output is valid, and can be read at any time.


EEC 180 | B. Baas | ECE Dept. | UC Davis 
2020/05/17  Lots of clarifying, simplifying, reordering, and formatting. (BB)
2019/05/25  Consistent wording that the  main clk may be either 25 or 50 MHz and other clarifications. (BB)
2019/05/20  Fixed typos (BB)
2019/02/12  Minor edits (BB)
Written by Mark Hildebrand and Bevan Baas