EEC280: High-Performance System Design

Prof. Vojin G. Oklobdzija
 Electrical and Computer Engineering Department
 University of California
 Davis

Reading Assignments

Week Subject Reading
Week No. 1

Introduction

Meyerson DAC presentation

Intorduction Chapter (Prof.)
Week No. 2 CMOS

Pass Transistor Design

 1. A. Masaki, "Deep-Submicron CMOS Warms Up to High-Speed Logic",

8. S. Whitaker, "Pass-Transistor Dual Value Logic for Low-Power CMOS"

Week No. 3 Logical Effort  Paper by Sutherland, Intro by Horowitz, Stanford EE313 Handouts:
Model Calibration and Optimal Gate Sizing, Logical Effort,
Gates with Lower LE and RC Model Limitations

Energy-Efficient Digital Circuit Design Chapter (pdf)
 
Week No. 4 Dynamic Logic, CMOS Domino, CVS, DCVS

1. Krambeck, C.M. Lee, H.S. Law, "High-Speed Compact Circuits with CMOS", IEEE Journal of Solid-State Circuits, Vol. SD-13, NO 3, June 1982.

3. V. G. Oklobdzija, R. K. Montoye, "Design-Performance Trade-Offs in CMOS-Domino Logic", IEEE Journal of Solid-State Circuits, Vol. SC-21, NO 2, April 1986.

4. Goncalves, H.J.DeMan, "NORA- A Race free Dynamic CMOS Technique for Pipelined Logic Structures", IEEE Journal of Solid-State Circuits, Vol. SC-18, No 3, June 1983.

5. L.G. Heller, et al, "Cascode Voltage Switch Logic : A Differential CMOS Logic Family", in 1984 Digest of Technical Papers, IEEE International solid-State Circuits Conference, February 1984.

6. K.M.Chu, D.L. Pulfrey,"A comparison of CMOS Circuit Techniques-Differential Cascode Voltage Switch Logic Versus Conventional Logic", IEEE Journal of solid-State Circuits, Vol. SC-22, No 4, August 1987.

 
Week No. 5

Pass-Transistor Logic:

CPL, DPL, DVL

1. S. Whitaker, "Pass-Transistor Dual Value Logic for Low-Power CMOS", Electronics, September 1983.

2. K. Yano, et al, "A 3.8-ns CMOS 16*16-b Multiplier using Complementary Pass-Transistor Logic", IEEE Journal of Solid-State Cirruits, Vol.25, No 2, April 1990.

3. K. Yano, et al, "Lean Integration Achieving a Quantum Leap in Performance and Cost of Logic LSIs", Proceeding of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.

4. M. Suzuki, et al, "A 1.5-ns 32-b CMOS ALU in Double Pass-Transistor Logic", Journal of Solid-State Circuits, Vol. 28. No 11, November 1993.

5. N. Ohkubo, et al, "A 4.4-ns CMOS 54*54-b Multiplier using Pass-Transistor Multiplexer", Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.

6. V. G. Oklobdzija and B. Duchene, "Pass-Transistor Dual Value Logic for Low-Power CMOS", Proceedings of the 1995 International Symposium on VLSI Technology, Taipei, Taiwan, May 31-June 2nd, 1995.

7. Dejan Markovic, Borivoje Nikolic, V. G. Oklobdzija, "General Method in Synthesis of Path-Transistor Circuits", Proceedings of the 22st International Conference on Microelectronics (MIEL'2000), Vol. 2, Nis, Serbia, 14-17 May, 2000.

8. F. S. Lai, W. Hwang, "Differential Cascode Voltage Switch with the Pass-Gate (DCVSPG) Logic Tree for High Performance CMOS Digital Systems", Proceedings of the 1993 International Symposium on VLSI Technology, Taipei, Taiwan, June2-4, 1995.

 
Week No. 6

Application of Logical Effort,

Low-Power Design

 1. V. G. Oklobdzija, Bart R. Zeydel, Hoang Dao, Sanu Mathew, Ram Krishnamurthy, "Energy-Delay Estimation Technique for High-Performance Microprocessor", Proceesing of the Symposium on Computer Arithmetic , 1063-6899, 2003.

2. A. Chandrakasan, R. Brodersen, "Minimizing Power Consumption in CMOS Circuits", IEEE Proceedings 1995.

3. T. Kuroda and T. Sakurai "Overview of Low-Power ULSI Circuit Techniques", IEICE Trans. Electronics, E78-C, No. 4, April 1995, pp.334-344, INVITED PAPER, Special Issue on Low-Voltage Low-Power Integrated Circuits.

 
Week No. 7

Advanced Topics on Logical Effort,

Low-Power Design

1. B. S. Amrutur, M. A. Horowitz,"Fast Low-Power Decoders for RAMs",IEEE Journal of Solid-State Circuits, Vol. 36, No. 10, October 2001.

2. P. Rezvani, M. Pedram,"A Fanout Optimization Algorithm Based on the Effort Delay Model",IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, Issue 12, December 2003.

1. A. Chandrakasan, R. Brodersen, "Minimizing Power Consumption in CMOS Circuits", IEEE Proceedings 1995.

2. T. Kuroda and T. Sakurai "Overview of Low-Power ULSI Circuit Techniques", IEICE Trans. Electronics, E78-C, No. 4, April 1995, pp.334-344, INVITED PAPER, Special Issue on Low-Voltage Low-Power Integrated Circuits.

3. Y. Sasaki, et al, "Multi-Level Pass-Transistor Logic for Low-Power ULSIs", Proceedings of the 1995 Low-Power Integrated Circuits.

5. C. Nagendra, et al, "A Comparison of the Power-Delay Characteristics of CMOS Adders", Proceedings of the International Workshop on Low-Power Design, 1994.

 

 
Week No. 8

Low-Power Design,

 

Digital system clocking

Clocked Storage Elements

1. C. Tan, et al, "Minimization of Power in VLSI Circuits Using Transistor Sizing, Input Ordering, and Statistical Power Estimation", Proceedings of the International Workshop on Low-Power Design, 1994.

2. M. Horowitz, et al, "Low-Power Digital Design", Proceedings of the 1994 IEEE Symposium on Low-Power Electronics, 1994.

3. H. Kojima, et al, "Power Analysis of a Programmable DSP for Architecture/Program Optimization", Proceedings of the 1995 Low-Power Symposium.

4. V. G. Oklobdzija, “Architectural Tradeoffs for Low Power”, International Symposium on Computer Architecture, Barcelona, SPAIN, June 27-July 1st, 1998.

 

Clocking:

1. Eby G. Friedman, "Clock Distribution Networks in VLSI Circuits and Systems", in IEEE Press, 1995.

2. Wagner, "Clock System Design", IEEE Design & Test of Computers, October 1988.

 

 
Week No. 9

Digital system clocking

Clocked Storage Elements 

3. S. H. Unger, C. Tan, "Clocking Schemes for High-Speed Digital Systems", IEEE Transactions on Computers, Vol C-35, No 10, October 1986.

4. V. Stojanovic, Oklobdzija V. G.,"Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems", IEEE Journal of Solid-State Circuits, Vol. 34, No. 4, April 1999.

5. M. Afghahi, C. Svensson, "A Unified Single-Phase Clocking Scheme for VLSI Systems", IEEE Journal of Solid-State Circuits, Vol 25, No 1, February 1990.

6. H. Partovi et al, "Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements", Proceeddings of 1996 IEEE International Solid-State Circuits Conference, San Francisco, California February 1996.

7. D. Dobberpuhl et al, "A 200MHz 64-b Dual-Issue CMOS Microprocessor", IEEE journal of Solid-State Circuits, Vol 27, No 11, November 1992.

8. B. J. Benschneider, et al, "A 300-MHz 64-b Quad-Issue CMOS RISC Microprocessor", IEEE Journal of Solid-State Circuits, Vol 30, No 11, November 1995.

9. Nikola Nedovic, Vojin G. Oklobdzija, William W. Walker, "A Clock Skew Absorbing Flip-Flop", IEEE International Solid-State circuits Conference, February 12, 2003.

10. Vojin G. Oklobdzija , "Issues in System on the Chip Clocking", Invited Paper, Proceedings of the IEEK System on Chip Design Conference, Seoul, Korea, November 5-6, 2003.

11. V. G. Oklobdzija,"Clocking and Clocked Storage Elements in a Multi-Gigahertz Environment", IBM, J. RES. & DEV. Vol. 47, No. 5/6, September/November 2003

 
Week No. 10 VLSI Arithmetic,

Energy-Delay relationship in digital circuits

1. Weinberger, J. L. Smith,"A Logic for High-Speed Addition", National Bureau of Standards, Circulation 591, p.3-12, 1958.

2. Sklanski, "Conditional-Sum Addition Logic", IRE Transaction on Electronic Computers, EC-9,pp.26-231, 1960.

3. V. G. Oklobdzija, E. R. Barnes, "Some Optimal Schemes for ALU Implementation in VLSI Technology", Proceedings of 7th Symposium on Computer Arithmetic, June 4-6, 1985, University of Illinois, Urbana, Illinois. 

4. V. G. Oklobdzija, Bart R. Zeydel, Hoang Dao, Sanu Mathew, Ram Krishnamurthy, "Energy-Delay Estimation Technique for High-Performance Microprocessor", Proceesing of the Symposium on Computer Arithmetic , 1063-6899, 2003.

5. C. S. Wallace, "A Suggestion for a Fast Multipliers", IEEE Transactions on Electronic Computers, EC-13, p.14-17, 1964.

6. L. Dadda, "Some Schemes for Parallel Multipliers", Alta Frequenza, Vol.34, p.349-356, March 1965.

7. V. G. Oklobdzija, D. Villeger, S. S. Liu, "A method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers using and Algorithmic Approach", IEEE Transaction on Computers, Vol.45, No.3, march 1996.

8. V. Oklobdzija, "High-Speed VLSI Arithmetic Units: Adders and Multipliers", in "Design of High-Performance Microprocessor Circuits", Book Chapter, Book edited by A. Chandrakasan, IEEE Press, 2000.

 

V. G. Oklobdzija, Bart Zeydel, "Power-Performance Characteristics of CMOS Adders" Chapter (pdf)