Our speaker program is now complete; we're adding titles and
abstracts as we receive them, and expect to post slides after the
workshop is done.
| Wednesday, 6 December |
| 7:30 AM | Continental Breakfast |
| 8:30 AM | Welcome |
| 8:45 AM | Session
1—Applications (Session
Chair: Andrew Chien)
- Partha
Kundu, Intel, On-Die Interconnects for Next Generation
CMPs [ abstract, slides (pdf), video ]
- Drew
Wingard, Sonics, Intelligent Interconnects for
Multicore SoCs
[ abstract, slides (pps), video ]
- Ivo Bolsens, Xilinx
[ abstract, slides (pdf), video ]
|
| 10:15 AM | Break |
| 10:45 AM | Session 2—Technology (Session Chair: David
Albonesi)
- Mark
Horowitz, Stanford, Scaling, Power and the Future of
CMOS
[ abstract, slides (pdf), video ]
- Shekhar
Borkar, Intel, Networks for Multi-core Chip—A
Controversial View
[ abstract, slides (pdf, ppt), video ]
- Ron
Ho, Sun, Interconnection Technologies for Large-Scale
Multiprocessors
[ abstract, slides
(pdf), video ]
|
| 12:15 AM | Lunch |
| 1:00 PM | Session
3—OCIN State of the Art I (Session
Chair: John Owens)
- José Duato,
Universidad Politécnica de Valencia, On-Chip Networks: Do We Need More Research? [ abstract, slides (pdf), video ]
- Chita Das, Penn
State, Exploring NoC Design Space for Multicore
Architectures
[ abstract, slides (pdf), video ]
- Bill Dally,
Stanford, Future Directions for On-Chip Interconnection
Networks
[ abstract, slides (pdf), video ]
|
| 2:30 PM | Poster Session 1 |
| 3:30 PM | Session 4—OCIN State of the Art II (Session
Chair: Steven Reinhardt)
- Li-Shiuan
Peh, Princeton, Low-power Interconnection Networks
[ abstract, slides (pdf), video ]
- Luca
Benini, DEIS Universitá di Bologna, Design
Automation for Networks-on-chip: Status and Outlook
[ abstract, slides (pdf), video ]
- Manolis
Katevenis, University of Crete, Towards Light-Weight
Intra-CMP Network Interfaces
[ abstract, slides (pdf), video ]
|
| 5:00 PM | Break |
| 5:30 PM | Panel/Discussion—OCIN Research Issues [ video ] |
| 6:30 PM | Dinner (Stanford Faculty Club) |
| 8:00 PM | Working Groups (Stanford Faculty Club) |
| 10:00 PM | Adjourn |
|
| Thursday, 7 December |
| 7:30 AM | Continental Breakfast |
| 8:30 AM | Working Groups (continued) |
| 10:00 AM | Poster Session 2 |
| 11:00 AM | Frederica
Darema, NSF, Directions in On-chip Networks [ video ]
Outbrief from working groups
- Technology and Circuits for On-Chip Networks [ slides (ppt, pdf), video ]
- Evaluation and Driving Applications for On-Chip Networks [ slides (ppt, pdf), video ]
- CAD and Design Tools for On-Chip Networks [ slides (ppt, pdf), video ]
- System Architecture for On-Chip Networks [ slides (ppt, pdf), video ]
- Research Directions for On-chip Network Microarchitectures
[ slides (ppt, pdf), video ]
|
| 12:30 PM | Lunch |
| 2:00 PM | Session 5—Prototyping (Session Chair: Christos Kozyrakis)
- Steve
Keckler, The University of Texas, Micronetwork-based
Processor Microarchitectures
[ abstract, slides (pdf), video ]
- Robert Mullins,
Cambridge, Communication-Centric Design
[ abstract, slides (pdf, ppt), video ]
- Michael
Taylor, UCSD, Scalar Operand Networks for Tiled Microprocessors [ abstract, slides (pdf, ppt), video ]
|
| 3:30 PM | Poster Session 3 |
| 4:00 PM | Wrapup, Bill Dally, Stanford [ slides (pdf, ppt), video ] |
| 4:15 PM | Break |
| 6:30 PM | Dinner
(California
Cafe, Palo Alto) |
| 9:00 PM | Adjourn |