EEC 281 - Homework/Project #2

Winter 2013

Work individually, but I strongly recommend working with someone in the class nearby so you can help each other when you get stuck, with consideration to the course collaboration policy. Please send me email if something isn't clear and I will update the assignment. Changes are logged at the bottom of this page.

Notes:

At the time the hwk/project is due, two things must be submitted:
1. A paper copy of everything [instructions], and
2. Electronic copies of only your code and testing files uploaded onto SmartSite (under "Assignments" not "Drop Box") in a tar or zip file.
*** Where three '*'s appear in the homework, perform the required test(s) and turn in a printout of either:
1. a table printed by your verilog testbench module listing all inputs and corresponding outputs,
2. a simvision waveform plot which shows (labeled and highlighted) corresponding inputs and outputs, or
3. verilog test code which compares the designed circuit and a simple reference circuit (using high-level functions such as "+"), and two copy & paste sections of text from your simulation's output (one for pass, and one for fail where you purposely make a slight change to your reference code to make it fail) that look something like this:
  Error: input=0101, out_module=11110000, out_ref=11110001
For all three options,
- Show your work of how you verified your simulation's outputs are correct or not,
- Test output must be copied & pasted from the simulator's output directly without any modifications whatsoever.
Your design and code must be easily readable, understandable, and well commented.
Do not include the problem statement in your submission, just your answers. Or if you really want to include it, show it in a different font such as italics.
Keep "hardware" modules separate from testing code. Instantiate a copy of your processing module(s) in your testing module (the highest level module) and drive the inputs and check the outputs from there.
If the problem requires synthesis, turn in paper copies of the following. Print in a way that is clear and easy to understand but conserves paper (multiple files per page, 8 or 9 point font, multiple columns). Edit sections with many repeating lines so they have only a few lines and replace with the comment: <many lines removed> .
1. dc_compile (or equivalent)
2. *.area file
3. *.log file; use something like dc_shell -f dc_compile | tee prac.log as shown on the DC tutorial page. Edit and reduce "Beginning Delay Optimization Phase" and "Beginning Area-Recovery Phase" sections.
4. *.pow file; summary only
5. *.tim file; first (longest) path only
Additional points beyond what are listed below. TotalProbPts is the sum of all points possible.
- [Up to TotalProbPts x 50%] point reduction for not accurately stating whether each design is fully functional, and stating the failing sections if any exist.
- [Up to TotalProbPts x 10%] point reduction if parts of different problems are mixed up together (makes grading much more difficult).
- [Up to TotalProbPts x 10%] extra credit may be given for especially thorough, well-documented, or insightful solutions.

For this homework/project, you may use the
always @(*)
verilog construct but first make sure Design Compiler is compatible with it.

[25 pts] The purpose of this problem is to familiarize you with the synthesis process and to give you a rough feeling for the size of a few simple circuits in our standard cell library's technology. Copy the files from the DC tutorial (see link on main EEC281 page) to get started. Synthesize the following blocks and report their total cell area. Do not include registers (flip-flops) in these blocks. Also, do not declare any wires or registers as "signed", but assume words are all 2's complement signed unless stated otherwise. No need to simulate or turn in any files other than the source verilog, but your verilog must compile correctly (run "make check").
For this problem, do not worry if designs do not meet timing (negative slack time). Report totals in a single table so it can be used as a note sheet in the future.
For this problem, do not submit the 5 synthesis reports listed above.

Blocks
a) [2 pts] bitwise OR of two 10-bit numbers (10-bit output)
b) [2 pts] 3:2 adder using verilog "&" "|", "^", "~".
Draw your circuit and the circuit output by DC.
c) [2 pts] 3:2 adder using verilog "+".
d) [3 pts] 10-bit adder (11-bit output). Use "+" in verilog.
e) [5 pts] an adder which adds 29 6-bit numbers using verilog "+" (i.e., something like, assign out = in0 + in1 + in2 + ...) and produces a 6-bit sum.
f) [5 pts] your 29-input adder from hwk/proj 1, problem 5.
g) [3 pts] 8-bit x 8-bit unsigned multiplier (16-bit output). Use "*" in verilog.
h) [3 pts] 16-bit x 16-bit unsigned multiplier (32-bit output). Use "*" in verilog.
[45 pts] Build a 6-bit x 6-bit non-Booth multiplier where both inputs are in signed 2's complement format. Register all inputs and outputs (to make synthesis timing accurate).
a) [10 pts] Draw the dot diagram including all adders
b) [25 pts] Write design in verilog, test with at least 15 test cases in addition to the ones listed below. Verify using method ***(3).
```
              0     x           0
              1     x     max pos
              1     x     max neg
        max pos     x           1
        max neg     x           1
        max pos     x     max pos
        max pos     x     max neg
        max neg     x     max pos
        max neg     x     max neg
        
```
c) [10 pts] Synthesize the design and state area. Submit *.area and *.tim (longest path only) reports only.
[45 pts] Build a 6-bit x 6-bit Booth-2 multiplier where both inputs are in signed 2's complement format. Register all inputs and outputs.
a) [10 pts] Draw the dot diagram including all adders
b) [25 pts] Same as problem 2(b)
c) [10 pts] Synthesize the design and state area. Submit *.area and *.tim (longest path only) reports only.

[65 pts] Build a complex multiplier using the unchanged non-Booth multiplier you built in Problem 2. The output must be of sufficient width for all possible input cases. Register all inputs and outputs.

a) [10 pts] Draw the dot diagram including all adders

b) [45 pts] Write design in verilog, test with at least 10 test cases in addition to the ones listed below. Verify using method ***(3).

        (     Re,      Im)  x  (     Re,      Im)
        (      0,       0)  x  (      0,       0)
        (max pos, max pos)  x  (      1,       0)
        (max neg, max neg)  x  (      1,       0)
        (      1,       0)  x  (max pos, max pos)
        (      1,       0)  x  (max neg, max neg)
        (max pos, max pos)  x  (max pos, max pos)
        (max pos, max pos)  x  (max neg, max neg)
        (max neg, max neg)  x  (max pos, max pos)
        (max neg, max neg)  x  (max neg, max neg)

c) [10 pts] Synthesize the design and state area. Submit *.area and *.tim (longest path only) reports only.

Updates:

2013/02/04  Posted

EEC 281 - Homework/Project #2

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