EEC 281 - Homework/Project #2

Winter 2013

Work individually, but I strongly recommend working with someone in the class nearby so you can help each other when you get stuck, with consideration to the course collaboration policy. Please send me email if something isn't clear and I will update the assignment. Changes are logged at the bottom of this page.

Notes:


For this homework/project, you may use the
  always @(*)
verilog construct but first make sure Design Compiler is compatible with it.

  1. [25 pts] The purpose of this problem is to familiarize you with the synthesis process and to give you a rough feeling for the size of a few simple circuits in our standard cell library's technology. Copy the files from the DC tutorial (see link on main EEC281 page) to get started. Synthesize the following blocks and report their total cell area. Do not include registers (flip-flops) in these blocks. Also, do not declare any wires or registers as "signed", but assume words are all 2's complement signed unless stated otherwise. No need to simulate or turn in any files other than the source verilog, but your verilog must compile correctly (run "make check").

    For this problem, do not worry if designs do not meet timing (negative slack time). Report totals in a single table so it can be used as a note sheet in the future.

    For this problem, do not submit the 5 synthesis reports listed above.

    Blocks

    a) [2 pts] bitwise OR of two 10-bit numbers (10-bit output)

    b) [2 pts] 3:2 adder using verilog "&" "|", "^", "~".
    Draw your circuit and the circuit output by DC.

    c) [2 pts] 3:2 adder using verilog "+".

    d) [3 pts] 10-bit adder (11-bit output). Use "+" in verilog.

    e) [5 pts] an adder which adds 29 6-bit numbers using verilog "+" (i.e., something like, assign out = in0 + in1 + in2 + ...) and produces a 6-bit sum.

    f) [5 pts] your 29-input adder from hwk/proj 1, problem 5.

    g) [3 pts] 8-bit x 8-bit unsigned multiplier (16-bit output). Use "*" in verilog.

    h) [3 pts] 16-bit x 16-bit unsigned multiplier (32-bit output). Use "*" in verilog.


  2. [45 pts] Build a 6-bit x 6-bit non-Booth multiplier where both inputs are in signed 2's complement format. Register all inputs and outputs (to make synthesis timing accurate).

    a) [10 pts] Draw the dot diagram including all adders

    b) [25 pts] Write design in verilog, test with at least 15 test cases in addition to the ones listed below. Verify using method ***(3).

                  0     x           0
                  1     x     max pos
                  1     x     max neg
            max pos     x           1
            max neg     x           1
            max pos     x     max pos
            max pos     x     max neg
            max neg     x     max pos
            max neg     x     max neg
            
    c) [10 pts] Synthesize the design and state area. Submit *.area and *.tim (longest path only) reports only.


  3. [45 pts] Build a 6-bit x 6-bit Booth-2 multiplier where both inputs are in signed 2's complement format. Register all inputs and outputs.

    a) [10 pts] Draw the dot diagram including all adders

    b) [25 pts] Same as problem 2(b)

    c) [10 pts] Synthesize the design and state area. Submit *.area and *.tim (longest path only) reports only.


  4. [65 pts] Build a complex multiplier using the unchanged non-Booth multiplier you built in Problem 2. The output must be of sufficient width for all possible input cases. Register all inputs and outputs.

    a) [10 pts] Draw the dot diagram including all adders

    b) [45 pts] Write design in verilog, test with at least 10 test cases in addition to the ones listed below. Verify using method ***(3).

            (     Re,      Im)  x  (     Re,      Im)
            (      0,       0)  x  (      0,       0)
            (max pos, max pos)  x  (      1,       0)
            (max neg, max neg)  x  (      1,       0)
            (      1,       0)  x  (max pos, max pos)
            (      1,       0)  x  (max neg, max neg)
            (max pos, max pos)  x  (max pos, max pos)
            (max pos, max pos)  x  (max neg, max neg)
            (max neg, max neg)  x  (max pos, max pos)
            (max neg, max neg)  x  (max neg, max neg)
            
    c) [10 pts] Synthesize the design and state area. Submit *.area and *.tim (longest path only) reports only.



Updates:

2013/02/04  Posted