Work individually, but I strongly recommend working with someone in the class nearby so you can help each other when you get stuck, with consideration to the Course Collaboration Policy. Please send me email if something isn't clear and I will update the assignment. Changes are logged at the bottom of this page.
Notes:
Do not include the problem statement in your submission, just your answers. Or if you really want to include it, show it in a different font such as italics.
Run all compiles with "medium" effort unless told otherwise. Do not modify the synthesis script except for functional purposes (e.g., to change or add source file names). There are many knobs to enhance synthesis results but that is not our focus. If you would like to improve the script, please talk to me and we can see if it makes sense to add it to the base script.
inA inB outExp outMantissa Correct? -------- -------- ------ -------------- -------- 10101100 00110101 110010 01100110100101 Y 00000101 10110101 101010 01010101010101 Y 01010100 11101010 010100 11010101100101 no
For this homework/project, you may use the "always @(*)" verilog construct but first make sure Design Compiler is compatible with it.
For this problem, do not worry if designs do not meet timing (negative slack time). Report totals in a single table so it can be used as a note sheet in the future.
For this problem, do not submit the 5 synthesis reports listed above.
b) [2 pts] 3:2 adder using verilog "&" "|",
"^", "~".
Draw your circuit and the circuit output by DC.
c) [2 pts] 3:2 adder using verilog "+".
d) [3 pts] 10-bit adder (11-bit output). Use "+" in verilog.
e) [5 pts] an adder which adds 29 6-bit numbers using verilog "+" (i.e., something like, assign out = in0 + in1 + in2 + ...) and produces a 6-bit sum.
f) [5 pts] your 29-input adder from hwk/proj 1, Problem 6. If your adder is not functional, improve it so it is at least synthesizable, synthesize it anyway, and write a note on your submission that it is not functional.
g) [3 pts] 8-bit x 8-bit unsigned multiplier (16-bit output). Use "*" in verilog.
h) [3 pts] 16-bit x 16-bit unsigned multiplier (32-bit output). Use "*" in verilog.
a) [10 pts] Draw the dot diagram including all adders
b) [25 pts] Write the design in verilog, test with at least 15 test cases in addition to the ones listed below. Verify using method ***(3).
0 x 0 1 x max pos 1 x max neg max pos x 1 max neg x 1 max pos x max pos max pos x max neg max neg x max pos max neg x max negc) [10 pts] Synthesize the design and state area. Submit *.area and *.tim (longest path only) reports only.
a) [5 pts] Same as problem 2(a)
b) [20 pts] Same as problem 2(b)
c) [10 pts] Same as problem 2(c)
a) [10 pts] Draw the dot diagram including all adders
b) [45 pts] Write the design in verilog, test with at least 10 test cases in addition to the ones listed below. Verify using method ***(3).
( Re, Im) x ( Re, Im) ( 0, 0) x ( 0, 0) (max pos, max pos) x ( 1, 0) (max neg, max neg) x ( 1, 0) ( 1, 0) x (max pos, max pos) ( 1, 0) x (max neg, max neg) (max pos, max pos) x (max pos, max pos) (max pos, max pos) x (max neg, max neg) (max neg, max neg) x (max pos, max pos) (max neg, max neg) x (max neg, max neg)c) [10 pts] Synthesize the design and state area. Submit *.area and *.tim (longest path only) reports only.
b) [30 pts] Implement the design in verilog and show that it correctly works for both values of skip. Verify using method ***(2).
2017/02/04 Posted