Work individually, but I strongly recommend working with someone in the class
nearby so you can help each other when you get stuck, with consideration
to the Course Collaboration Policy.
Please send me email if something isn't clear and I will update the
assignment. Changes are logged at the bottom of this page.
When due, two copies of
1) all hardware and testing code you wrote, and
2) all other requested files,
must be submitted via:
A paper copy which is graded
An electronic copy used only as a backup
When due, two copies of 1) all hardware and testing code you wrote, and 2) all other requested files, must be submitted via:
A paper copy which is graded [instructions], and
An electronic copy used only as a backup
Label directories or files so it is clear to which problem they belong. For example, prob1.v, prob1.vt,...
Diagrams. If a problem requires a diagram, include details such as datapath, memory, control, I/O, pipeline stages, word widths in bits, etc. There must be enough detail so that the exact functional operation of the block can be determined by someone with your diagram and explanation, and a reasonable knowledge of what simple blocks do. A satisfactory diagram may require multiple pages of paper taped together into a single large sheet.
Verilog. If a problem requires a verilog design, turn in paper copies of both hardware and test verilog code.
a table printed by your verilog testbench module listing all inputs and corresponding outputs,
a simvision waveform plot which shows (labeled and highlighted) corresponding inputs and outputs, or
test code which compares the designed circuit and a simple
reference circuit (using high-level functions such as "+"),
and two copy & paste sections of text from your
simulation's output (one for pass, and one for fail where you
purposely make a very small change to your
designed hardware circuit or your reference circuit,
to force the comparison to fail) that look something like this:
Error: input=0101, out_module=11110000, out_ref=11110001
For 1 and 3, the output must be copied & pasted directly from the simulator's output without any modifications.
In all cases, Show how you verified the correctness of your simulation's outputs.
Synthesis. If a problem requires synthesis, turn in paper copies of the following. Print in a way that results are easy to understand but conserves paper (multiple files per page, 8 or 9 point font, multiple columns). Delete sections of many repeated lines with a few copies of the line plus the comment: <many lines removed> .
Run all compiles with "medium" effort unless told otherwise. Do not modify the synthesis script except for functional purposes (e.g., to change or add source file names).
Functionality. For each design problem, you must write by hand 1) whether the design is fully functional, and 2) the failing sections if any exist.
Point deductions/additions. TotalProbPts is the sum of all points possible.
inA inB outExp outMantissa Correct? -------- -------- ------ -------------- -------- 10101100 00110101 110010 01100110100101 Y 00000101 10110101 101010 01010101010101 Y 01010100 11101010 010100 11010101100101 no
Clarity. For full credit, your submission must be easily readable, understandable, and well commented.
For this homework/project, you may use the "always @(*)" verilog construct but first make sure Design Compiler is compatible with it.
[25 pts] The purpose of this problem is to familiarize you with the synthesis process and to give you a rough feeling for the size of a few simple circuits in our standard cell library's technology. Copy the files from the DC tutorial (see link on main EEC281 page) to get started. Synthesize the following blocks and report their total cell area. Do not include registers (flip-flops) in these blocks. Also, do not declare any wires or registers as "signed", but assume words are all 2's complement signed unless stated otherwise. No need to simulate, but your verilog must compile correctly (run "make check"). Also, for this problem, do not worry if designs do not meet timing (negative slack time).
Turn in: 1) source verilog, 2) totals in a single table so it can be used as a note sheet in the future. Do not submit any output synthesis reports.
b) [2 pts] 3:2 adder using verilog "&" "|",
Draw your circuit and the circuit output by DC.
c) [2 pts] 3:2 adder using verilog "+".
d) [3 pts] 10-bit adder (11-bit output). Use "+" in verilog.
e) [5 pts] an adder which adds 11 5-bit numbers using verilog "+" (i.e., something like, assign out = in0 + in1 + in2 + ...) and produces a 5-bit sum.
f) [5 pts] your 11-input adder from hwk/proj 1, Problem 7. If your adder is not functional, improve it so it is at least synthesizable, synthesize it anyway, and write a note on your submission that it is not functional.
g) [3 pts] 8-bit x 8-bit unsigned multiplier (16-bit output). Use "*" in verilog.
h) [3 pts] 16-bit x 16-bit unsigned multiplier (32-bit output). Use "*" in verilog.
a) [10 pts] Draw the dot diagram including all adders
b) [25 pts] Write the design in verilog, test with at least 15 test cases in addition to the ones listed below. Verify using method ***(3).
0 x 0 1 x max pos 1 x max neg max pos x 1 max neg x 1 max pos x max pos max pos x max neg max neg x max pos max neg x max negc) [10 pts] Synthesize the design and state area. Submit *.area and *.tim (longest path only) reports only.
a) [5 pts] Same as problem 2(a)
b) [20 pts] Same as problem 2(b)
c) [10 pts] Same as problem 2(c)
[40 pts] Design a state machine with the following states and actions. Details not specified should be chosen by you and stated in your submission.
IDLE state is entered when reset is high at any time.
The output shutter is always zero when in the IDLE state.
The machine transitions to CAMERA_ON after 3 cycles.
While in CAMERA_ON state, the output signal shutter is pulsed
cycle 1: shutter=1
cycle 2: shutter=0
cycle 3: shutter=0
cycle 4: shutter=1
cycle 5: shutter=0
cycle 6: shutter=0
The machine transitions to PROCESS in the 7th cycle.
b) [30 pts] Implement the design in verilog and show that it correctly works for both values of skip. Verify using method ***(2).