Work individually, but I strongly recommend working with someone in the class nearby so you can help each other when you get stuck, with consideration to the Course Collaboration Policy. Please send me email if something isn't clear and I will update the assignment. Changes are logged at the bottom of this page.
Notes:
When due, two copies of 1) all hardware and testing code you wrote, and 2) all other requested files, must be submitted via:
A paper copy which is graded [instructions], and
An electronic copy used only as a backup uploaded to Canvas (under "Assignments") in a tar or zip file.
Label directories or files so it is clear to which problem they belong. For example, prob1.v, prob1.vt,...
Diagrams. If a problem requires a diagram, include details such as datapath, memory, control, I/O, pipeline stages, word widths in bits, etc. There must be enough detail so that the exact functional operation of the block can be determined by someone with your diagram and explanation, and a reasonable knowledge of what simple blocks do. A satisfactory diagram may require multiple pages of paper taped together into a single large sheet.
Verilog. If a problem requires a verilog design, turn in paper copies of both hardware and test verilog code.
a table printed by your verilog testbench module listing all inputs and corresponding outputs,
a simvision waveform plot which shows (labeled and highlighted) corresponding inputs and outputs, or
verilog
test code which compares the designed circuit and a simple
reference circuit (using high-level functions such as "+"),
and two copy & paste sections of text from your
simulation's output (one for pass, and one for fail where you
purposely make a very small change to your
designed hardware circuit or your reference circuit,
to force the comparison to fail) that look something like this:
Error: input=0101, out_module=11110000, out_ref=11110001
For 1 and 3, the output must be copied & pasted directly from the simulator's output without any modifications.
In all cases, Show how you verified the correctness of your simulation's outputs.
Synthesis. If a problem requires synthesis, turn in paper copies of the following. Print in a way that results are easy to understand but conserves paper (multiple files per page, 8 or 9 point font, multiple columns). Delete sections of many repeated lines with a few copies of the line plus the comment: <many lines removed> .
Run all compiles with "medium" effort unless told otherwise. Do not modify the synthesis script except for functional purposes (e.g., to change or add source file names).
Functionality. For each design problem, you must write by hand 1) whether the design is fully functional, and 2) the failing sections if any exist.
Point deductions/additions. TotalProbPts is the sum of all points possible.
inA inB outExp outMantissa Correct? -------- -------- ------ -------------- -------- 10101100 00110101 110010 01100110100101 Y 00000101 10110101 101010 01010101010101 Y 01010100 11101010 010100 11010101100101 no
Clarity. For full credit, your submission must be easily readable, understandable, and well commented.
If you would like to use your own algorithm, that's great. Otherwise, you might try coding an algorithm that works something like this:
a) [15 pts] Write the described function in matlab.
b) [5 pts] Assuming your function is called "numppterms", run the following bit of matlab code (a few points need fixing), and report the Total Sum for all numbers 0.5 – 100.00 .
StepSize = 0.5; NumTermsArrayPos = zeros(1, 100/StepSize); % small speedup if init first for k = StepSize : StepSize : 100, NumTermsArrayPos(k/StepSize) = numppterms(k); end fprintf('Total sum for +0.5 - +100.00 = %i\n', sum(NumTermsArrayPos)); figure(1); clf; plot(StepSize:StepSize:100, NumTermsArrayPos, 'x'); axis([0 101 0 1.1* max(NumTermsArrayPos)]); xlabel('Input number'); ylabel('Number of partial product terms');
coeff = [17 –90 241 902 241 –90 17];Assume the coefficients can not be scaled larger, but they can be scaled smaller (up to 50% smaller) and the gain change can be compensated elsewhere. This implementation works with integers only, so round(·) scaled coefficients.
a) [5 pts] How many partial products are necessary to implement the FIR filter with the given coefficients?
b) [5 pts] See if a scaling for the coefficients exists such that the filter can be built with fewer partial products. Find the scaling that yields the minimum number of partial products.
c) [5 pts] Turn in a plot of the number of required partial products vs. the scaling factor. The plot should look something like the bogus results this matlab code generates.
figure(1); clf; plot(0.5:0.001:1.0, round(5* rand(1,501)+1), 'x'); axis([0.45 1.05 0 6.5]); xlabel('Scaling factor'); ylabel('Number of partial product terms'); title('EEC 281, Hwk/proj 2, Problem 3, Plot of bogus results');d) [15 pts] Draw dot diagrams showing how the partial products would be added (include sign extension) for the optimized coefficients you found in (b), using the FIR architecture shown below and an 8-bit 2's complement input word. Use 4:2, 3:2, and half adders as necessary and no need to design the final stage carry-propagate adder.
in_theta input
12-bit fixed-point unsigned where:
0000_0000_0000 = 0.000 radians, and
1111_1111_1111 = 2π × (4095/4096) radians
reset input
out_real, out_imag outputs
each are 16-bit fixed-point 2's complement.
Generate all 2^12 possible theta inputs [0, 2π) in verilog
Calculate the e^{jθ} output for each theta with your verilog design
Output both the a) theta input and b) verilog output to a
plain text
matlab-readable *.m file.
For example, a file such as:
theta(1) = 0; re(1) = 64; im(1) = 0; % index 1 = angle 0
unfortunately since matlab can not have index = 0
theta(2) = 1; re(2) = 64; im(2) = 6;
theta(3) = 2; re(3) = 63; im(3) = 12;
where values can be printed out and then re-scaled in matlab however it
is most convenient.
Another possible format is:
theta(0+1) = 0; out_ver(1) = 64 + j * 0; % index 1 = angle 0
unfortunately since matlab can not have index = 0
theta(1+1) = 1; out_ver(2) = 64 + j * 6;
theta(2+1) = 2; out_ver(3) = 63 + j * 12;
Suggestion: print integers in verilog. Use "signed" reg's only for the printf statement.
Compare a) verilog output and b) exp(j*theta) using difff.m in matlab.
With a lookup table(s) for all values (largest area)
With lookup table(s) that cover no more than π/4, or one-eighth of the total 0–2π range and utilize additional logic to compute outputs for the entire span of 0–2π .
Use symmetry properties of the sin() and cos() such as the ones in the table found on this wikipedia page.
Same as design #2 but where outputs for odd theta inputs are linearly-interpolated between samples from the lookup table(s) and the system has a throughput of one calculation for every two clock cycles. The goal is smaller area.
For each of your three designs, submit (a) through (c) below. When submitting the verilog file of your lookup tables, print only the first ~15 lines and the last ~15 lines and insert the comment "<Many lines removed>" for lines you deleted.
c) [10 pts] Synthesize each of the three designs at a minimum of 3 different cycle time values and report the area for each.
NEXT TIME: Synthesize at these frequencies: 1) a very long cycle time, e.g., 1 ms = 1 KHz (minimum area); 2) a very short cycle time, e.g., 0.1 ns = 10 GHz; and 3) the cycle time achieved in the synthesis run for #2 × 1.5
No points are possible for (b) or (c) unless the design is fully functional and without synthesis errors or serious warnings.
Updates: 2018/03/03 Posted 2018/03/10 Clarifications in problem 3