EEC 281 - Homework/Project #1

Work individually, but I strongly recommend working with someone in the class nearby so you can help each other when you get stuck, with consideration to the course collaboration policy. Please send me email if something isn't clear and I will update the assignment. Changes are logged at the bottom of this page.

Notes:

• At the time the hwk/project is due, two things must be submitted:
  1. A paper copy of everything [instructions], and
  2. Electronic copies of only your code and testing files uploaded onto SmartSite (under "Assignments" not "Drop Box") in a tar or zip file.

• *** Where three '*'s appear in the homework, perform the required test(s) and turn in a printout of either:
  1. a table printed by your verilog testbench module listing all inputs and corresponding outputs,
  2. a simvision waveform plot which shows (labeled and highlighted) corresponding inputs and outputs, or
  3. verilog test code which compares the designed circuit and a simple reference circuit (using high-level functions such as "+"), and two copy & paste sections of text from your simulation's output (one for pass, and one for fail where you purposely make a slight change to your reference code to make it fail) that look something like this:
     Error: input=0101, out_module=11110000, out_ref=11110001
  For all three options,
  • Show your work of how you verified your simulation's outputs are correct or not,
  • Test output must be copied & pasted from the simulator's output directly without any modifications whatsoever.

• Your design and code must be easily readable, understandable, and well commented.

  Do not include the problem statement in your submission, just your answers. Or if you really want to include it, show it in a different font such as italics.

• Keep "hardware" modules separate from testing code. Instantiate a copy of your processing module(s) in your testing module (the highest level module) and drive the inputs and check the outputs from there.

• If the problem requires synthesis, turn in paper copies of the following. Print in a way that is clear and easy to understand but conserves paper (multiple files per page, 8 or 9 point font, multiple columns). Edit sections with many repeating lines so they have only a few lines and replace with the comment: <many lines removed> .
  1. dc_compile (or equivalent)
  2. *.area file
  3. *.log file; use something like dc_shell -f dc_compile | tee prac.log as shown on the DC tutorial page. Edit and reduce "Beginning Delay Optimization Phase" and "Beginning Area-Recovery Phase" sections.
  4. *.pow file; summary only
  5. *.tim file; first (longest) path only

• Additional points beyond what are listed below. TotalProbPts is the sum of all points possible.
  • [Up to TotalProbPts x 50%] point reduction for not accurately stating whether each design is fully functional, and stating the failing sections if any exist.

  • [Up to TotalProbPts x 10%] point reduction if parts of different problems are mixed up together (makes grading much more difficult).

  • [Up to TotalProbPts x 10%] extra credit may be given for especially thorough, well-documented, or insightful solutions.

1. [35 pts] Design and write the verilog for a block that adds three 5-bit numbers into a 2's complement output that is sufficiently large to represent all inputs but with no extra bits. Use one stage of 3:2 carry-save adders and one carry-propagate adder (CPA) using a "+" in verilog. The three inputs are in the following formats:
   • a is in 2's complement 2.3 format
   • b is in 2's complement 4.1 format
   • c is in unsigned 5.0 format

   a) [2 pts] How many bits does the output have and where is its decimal point?

   b) [4 pts] Show the adder's dot diagram.

   c) [3 pts] What is the output's minimum attainable negative value (most negative)?

   d) [3 pts] What is the output's minimum attainable positive value?

   e) [3 pts] What is the output's maximum attainable positive value?

   f) [20 pts] Test the circuit over at least 15 input values (including all extreme cases). Turn in ***, opt. 1

   
                          5     +-------+
                  a ------/-----|       |   
                          5     |       |     ?
                  b ------/-----|   +   |-----/------ out
                          5     |       |
                  c ------/-----|       |
                                +-------+
      

2. [35 pts] Design and write the verilog for a block that performs floating point to fixed point number conversion. The floating point input has a 6-bit signed, 2's complement mantissa in "2.4" format and a 3-bit 2's complement integer exponent. The fixed point number (output) has enough bits to fully represent the converted floating point number, but no more.
   a) [6 pts] How many bits does the fixed-point output have and where is its decimal point?
   b) [3 pts] What is the output's minimum attainable negative value?
   c) [3 pts] What is the output's minimum attainable positive value?
   d) [3 pts] What is the output's maximum attainable positive value?
   e) [20 pts] Test the circuit over at least 15 input values (including extreme cases). Turn in ***, opt. 1

   
                          6     +--------+
           mantissa ------/-----| float  |     ?
                                |  to    |-----/------ out
                exp ------/-----| fixed  |
                          3     +--------+
      

   [35 pts] Design and write the verilog for a block that performs fixed-point to floating-point number conversion. The input fixed-point number has 7 bits and is in "3.4" 2's complement notation. The floating point output has a 3-bit 2's complement integer mantissa and a 2's complement exponent.

   Keep the maximum possible number of bits from the input in the output mantissa. For example in base ten, 3.641 x 10^4 is much better than 0.036 x 10^6. Note that for some input values, the output may not be able to represent all bits in the input and it may be necessary to reduce the number of bits through rounding or truncation. Truncation is simpler, so use it for this problem. The output must never be denormalized.

   a) [6 pts] How many bits are required for the exponent?

   b) [3 pts] What is the output's minimum attainable negative value?

   c) [3 pts] What is the output's minimum attainable positive value?

   d) [3 pts] What is the output's maximum attainable positive value?

   e) [20 pts] Test the circuit over at least 15 input values (including extreme cases). Turn in ***, opt. 1

   
                                +--------+     3
                          7     | fixed  |-----/----- mantissa
                 in ------/-----|  to    |
                                | float  |-----/----- exp
                                +--------+     ?
      

   [40 pts] As mentioned in class, there are a number of ways to design a 4:2 adder.

   a) [5 pts] Using the diagram for the 4:2 given below and the truth table below, fill out the truth table with the values that must be a certain value for the circuit to operate correctly. Leave others blank. A few of these required values have been filled in.

   
                                 a b c d
                                 | | | |
                                 | | | |
                                +--------+
                                |        |
                           co --|  4:2   |-- ci
                                |        |
                                +--------+
                                   |  |  
                                   |  |  
                                  c1  s  
   
             inputs    outputs
                   c | c c
           a b c d i | o 1 s
          -----------+-------
           0 0 0 0 0 | 0 0 0
           0 0 0 0 1 | 0 0 1
           0 0 0 1 0 |     1
           0 0 0 1 1 |     0
           0 0 1 0 0 |     1   
           0 0 1 0 1 |         
           0 0 1 1 0 |         
           0 0 1 1 1 |         
           0 1 0 0 0 |         
           0 1 0 0 1 |         
           0 1 0 1 0 |         
           0 1 0 1 1 |         
           0 1 1 0 0 |         
           0 1 1 0 1 |         
           0 1 1 1 0 |         
           0 1 1 1 1 |         
           1 0 0 0 0 |         
           1 0 0 0 1 |         
           1 0 0 1 0 |         
           1 0 0 1 1 |         
           1 0 1 0 0 |         
           1 0 1 0 1 |         
           1 0 1 1 0 |         
           1 0 1 1 1 |         
           1 1 0 0 0 |         
           1 1 0 0 1 |         
           1 1 0 1 0 |         
           1 1 0 1 1 |         
           1 1 1 0 0 |         
           1 1 1 0 1 |         
           1 1 1 1 0 |         
           1 1 1 1 1 | 1 1 1
   
   
      

   b) [5 pts] Write the verilog for a Full Adder module using xor, and, or, inv operators. Also write the verilog for a 4:2 adder module using two full adder cells.

   c) [10 pts] Draw a dot diagram and write the verilog for a fast adder with six 4-bit signed 2's complement inputs and a 6-bit output. Compresses the inputs in carry-save form using your 4:2 and 3:2 adder modules, and add the final "carry" and "save" words using a "+" operator in verilog.

   d) [20 pts] Write a testbench module which instantiates the six-input adder module and test the circuit over the input values shown here. Turn in ***

           =   0 +   0 +   0 +   0 +  0 +  0
           =   1 +   0 +   0 +   0 +  0 +  0
           =   0 +   1 +   0 +   0 +  0 +  0
           =   0 +   0 +   1 +   0 +  0 +  0
           =   0 +   0 +   0 +   1 +  0 +  0
           =   0 +   0 +   0 +   0 +  1 +  0
           =   0 +   0 +   0 +   0 +  0 +  1
           =  -1 +   0 +   0 +   0 +  0 +  0
           =   0 +  -1 +   0 +   0 +  0 +  0
           =   0 +   0 +  -1 +   0 +  0 +  0
           =   0 +   0 +   0 +  -1 +  0 +  0
           =   0 +   0 +   0 +   0 + -1 +  0
           =   0 +   0 +   0 +   0 +  0 + -1
           =   7 +   0 +   0 +   0 +  0 +  0
           =   0 +   7 +   0 +   0 +  0 +  0
           =   0 +   0 +   7 +   0 +  0 +  0
           =   0 +   0 +   0 +   7 +  0 +  0
           =   0 +   0 +   0 +   0 +  7 +  0
           =   0 +   0 +   0 +   0 +  0 +  7
           =  -8 +   0 +   0 +   0 +  0 +  0
           =   0 +  -8 +   0 +   0 +  0 +  0
           =   0 +   0 +  -8 +   0 +  0 +  0
           =   0 +   0 +   0 +  -8 +  0 +  0
           =   0 +   0 +   0 +   0 + -8 +  0
           =   0 +   0 +   0 +   0 +  0 + -8
           =   1 +   1 +   1 +   1 +  1 +  1
           =  -1 +  -1 +  -1 +  -1 + -1 + -1
           =   1 +   2 +   3 +   4 +  5 +  6
           =   6 +   5 +   5 +   5 +  5 +  5
           =  -7 +  -5 +  -5 +  -5 + -5 + -5
           

   [35 pts] Design a block which adds 29 single-bit numbers, but where each input is not a standard binary number—instead each input represents –1 or +1. A zero input is –1 and a one input is +1. So the sum ranges from [–29, +29] and the output of the adder is to be represented by a 2's complement number sufficiently wide to represent all input combinations. This is an important structure in a CDMA transmitter which we will discuss later in the quarter. You may use 4:2, 3:2, and half adders (implemented as submodules however your wish; e.g., wire, reg, table) to add the inputs efficiently. Use only one carry-propagate adder, which you can implement with a "+" or "–" in verilog.

   
                                    +-------+
                              29    |       |     ?
                     in ------/-----|   +   |-----/------ out
                                    |       |
                                    +-------+
     

   a) [20 pts] Draw a "dot diagram" for an efficient adder.

   b) [5 pts] Total up and state how much hardware (in area) your design requires in units of 3:2 adders assuming a 4:2 adder costs the same as two 3:2 adders and a half adder costs 0.5 3:2 adders.

   c) [10 pts] Write your design in verilog, test it, and turn in ***. You may find these as helpful starting points: prob1.v, prob1_ref.v, and prob1.vt.

2013/01/17         Posted.