EEC 281  Homework/Project #1
Winter 2017
Work individually, but I strongly recommend working with someone in the class
nearby so you can help each other when you get stuck, with consideration
to the Course Collaboration Policy.
Please send me email if something isn't clear and I will update the
assignment. Changes are logged at the bottom of this page.
Notes:
 At the time the hwk/project is due, two things must be submitted:
 A paper copy of everything
[instructions], and
 Electronic copies of only the code and testing files you
wrote (no generated files) uploaded onto
SmartSite (under "Assignments"
not "Drop Box") in a tar or zip file.
 *** Where three '*'s appear in the homework, perform the required
test(s) and turn in a printout of either:
 a table
printed by your verilog testbench module listing all inputs
and corresponding outputs,
 a simvision
waveform plot which shows (labeled and
highlighted) corresponding inputs and outputs, or
 verilog
test code which compares the designed circuit and a simple
reference circuit (using highlevel functions such as "+"),
and two copy & paste sections of text from your
simulation's output (one for pass, and one for fail where you
purposely make a very small change to your
designed hardware circuit or your reference circuit,
to force the comparison to fail) that look something like this:
Error: input=0101, out_module=11110000, out_ref=11110001
For all three options,
 Show your work of how you verified your simulation's outputs
are correct or not,
 Test output must be copied & pasted from the simulator's
output directly without any modifications whatsoever.
 For each design problem, you must
1) state whether the design is fully functional, and
2) state the failing sections if any exist.
 Your design and code must be easily readable, understandable,
and well commented.
Do not include the problem statement in your submission, just your
answers. Or if you really want to include it, show it in a different
font such as italics.
 Keep "hardware" modules separate from testing code. Instantiate a
copy of your processing module(s) in your testing module (the highest
level module) and drive the inputs and check the outputs from there.

If a problem requires a diagram, include details such as datapath,
memory, control, I/O, pipeline stages, and word widths in bits. There
must be enough detail so that the exact functional operation of
the block can be determined by someone with your diagram and explanation,
and a reasonable knowledge of what simple blocks do. A satisfactory
diagram may require multiple pages of paper taped together.

If a problem requires a verilog design, turn in paper copies of both
hardware and test verilog code.
 If a problem requires synthesis, turn in paper copies of the following.
Print in a way that results are easy to understand but conserves
paper (multiple files per page, 8 or 9 point font, multiple columns).
Delete sections of many repeated lines with a few copies of the line plus
the comment: <many lines removed> .
 dc_compile (or equivalent)
 *.area file
 *.log file;
Edit and reduce "Beginning Delay Optimization Phase"
and "Beginning AreaRecovery Phase" sections.
 *.pow file; summary only
 *.tim file; first (longest) path only
Run all compiles with "medium" effort unless told otherwise.
Do not modify the synthesis script except for functional purposes
(e.g., to change or add source file names). There are many
knobs to enhance synthesis results but that is not our focus.
If you would like to improve the script, please talk to me and we can see
if it makes sense to add it to the base script.
 Additional points beyond what are listed below.
TotalProbPts is the sum of all points possible.
Total: 180 points
Before getting started, you should go through the verilog notes located
under Course Readings on the course home page.
 [35 pts] Design and write the verilog for a block that adds three
4bit numbers into a 2's complement output that is sufficiently large to
represent all inputs but with no extra bits. Use one stage of 3:2
carrysave adders and one carrypropagate adder (CPA) using a "+"
in verilog. The three inputs are as follows:
 a is in 2's complement 2.2 format
 b is in unsigned 3.1 format
 c is in signmagnitude format where the magnitude portion
is in 3.0 format
 a) [2 pts] How many bits does the output have and where
is its decimal point?
 b) [4 pts] Show the adder's dot diagram.
 c) [3 pts] What is the output's minimum attainable negative value
(most negative)?
 d) [3 pts] What is the output's minimum attainable positive value?
 e) [3 pts] What is the output's maximum attainable positive value?
 f) [20 pts] Test the circuit over at least 15 input values (including
extreme cases). Turn in ***, opt. 1
4 ++
a / 
4   ?
b / + / out
4  
c / 
++
 [35 pts] Design and write the verilog for a block that performs floating
point to fixed point number conversion. The floating point
input has a 7bit signed, 2's complement mantissa in
"4.3" format and a 3bit unsigned integer exponent.
The fixed point output has enough bits to fully represent
the converted floating point number, but no more.
 a) [6 pts] How many bits does the fixedpoint output have and where
is its decimal point?
 b) [3 pts] What is the output's minimum attainable negative value?
 c) [3 pts] What is the output's minimum attainable positive value?
 d) [3 pts] What is the output's maximum attainable positive value?
 e) [20 pts] Test the circuit over at least 15 input values (including
extreme cases). Turn in ***, opt. 1
7 ++
mantissa / float  ?
 to / out
exp / fixed 
3 ++
 [35 pts] Design and write the verilog for a block that performs
fixedpoint to floatingpoint number conversion. The input fixedpoint
number has 7 bits and is in "5.2" 2's complement notation.
The floating point output has a 4bit "3.1" 2's complement
mantissa and a 2's complement integer exponent.
Normalize the output mantissa—the output must never be denormalized.
Also keep the maximum possible number of bits from the input in the output
mantissa.
Note that for some input values, the output will not be able to
represent all bits in the input and it will be necessary to reduce the
number of bits through rounding or truncation. Truncation is simpler,
so use it for this problem.
 a) [6 pts] How many bits are required for the exponent?
 b) [3 pts] What is the output's minimum attainable negative value
(most negative)?
 c) [3 pts] What is the output's minimum attainable positive value?
 d) [3 pts] What is the output's maximum attainable positive value?
 e) [20 pts] Test the circuit over at least 15 input values (including
all extreme cases). Turn in ***, opt. 1
++ 4
7  fixed / mantissa
in / to 
 float / exp
++ ?
 [15 pts] As mentioned in class, there are a number of ways to design a
4:2 adder.
 a) [10 pts] Using the diagram for the 4:2 given below and the truth
table below, fill out the truth table with the values that must
be a certain value (0 or 1) for the circuit to operate correctly.
Leave others blank. A few of these required values have been filled in.
a b c d
   
   
++
 
co  4:2  ci
 
++
 
 
c1 s
inputs  outputs
c  c c
a b c d i  o 1 s
+
0 0 0 0 0  0 0 0
0 0 0 0 1  0 0 1
0 0 0 1 0  1
0 0 0 1 1  0
0 0 1 0 0  1
0 0 1 0 1 
0 0 1 1 0 
0 0 1 1 1 
0 1 0 0 0 
0 1 0 0 1 
0 1 0 1 0 
0 1 0 1 1 
0 1 1 0 0 
0 1 1 0 1 
0 1 1 1 0 
0 1 1 1 1 
1 0 0 0 0 
1 0 0 0 1 
1 0 0 1 0 
1 0 0 1 1 
1 0 1 0 0 
1 0 1 0 1 
1 0 1 1 0 
1 0 1 1 1 
1 1 0 0 0 
1 1 0 0 1 
1 1 0 1 0 
1 1 0 1 1 
1 1 1 0 0 
1 1 1 0 1 
1 1 1 1 0 
1 1 1 1 1  1 1 1
 b) [5 pts] Write the verilog for a Full Adder module using xor, and,
or, inv operators. Also write the verilog for a
4:2 adder module using two full adder cells.
Turn in *** option 1.
 [25 pts] Sixinput adder
 a) [10 pts] Draw a dot diagram and write the verilog for a fast
adder with six 4bit signed inputs and a 6bit output.
Compresses the inputs in carrysave form using your 4:2 and 3:2
adder modules, and add the final "carry" and "save" words using a
"+" operator in verilog.
 b) [15 pts] Write a testbench module which instantiates the
sixinput adder module and test the circuit over the input
values shown: Turn in ***
= 0 + 0 + 0 + 0 + 0 + 0
= 1 + 0 + 0 + 0 + 0 + 0
= 0 + 1 + 0 + 0 + 0 + 0
= 0 + 0 + 1 + 0 + 0 + 0
= 0 + 0 + 0 + 1 + 0 + 0
= 0 + 0 + 0 + 0 + 1 + 0
= 0 + 0 + 0 + 0 + 0 + 1
= 1 + 0 + 0 + 0 + 0 + 0
= 0 + 1 + 0 + 0 + 0 + 0
= 0 + 0 + 1 + 0 + 0 + 0
= 0 + 0 + 0 + 1 + 0 + 0
= 0 + 0 + 0 + 0 + 1 + 0
= 0 + 0 + 0 + 0 + 0 + 1
= 7 + 0 + 0 + 0 + 0 + 0
= 0 + 7 + 0 + 0 + 0 + 0
= 0 + 0 + 7 + 0 + 0 + 0
= 0 + 0 + 0 + 7 + 0 + 0
= 0 + 0 + 0 + 0 + 7 + 0
= 0 + 0 + 0 + 0 + 0 + 7
= 8 + 0 + 0 + 0 + 0 + 0
= 0 + 8 + 0 + 0 + 0 + 0
= 0 + 0 + 8 + 0 + 0 + 0
= 0 + 0 + 0 + 8 + 0 + 0
= 0 + 0 + 0 + 0 + 8 + 0
= 0 + 0 + 0 + 0 + 0 + 8
= 1 + 1 + 1 + 1 + 1 + 1
= 1 + 1 + 1 + 1 + 1 + 1
= 1 + 2 + 3 + 4 + 5 + 6
= 6 + 5 + 5 + 5 + 5 + 5
= 7 + 5 + 5 + 5 + 5 + 5
 [35 pts] Design a block which adds 29 singlebit numbers, where
each input is not a standard binary number—but instead each wire
represents 1 or +1. A zero input is 1 and a one input is +1.
The output of the adder is a 2's complement number sufficiently wide
to represent all input combinations. This is an important structure
in a CDMA transmitter.
You may use 4:2, 3:2, and half adders (implemented as submodules however
you wish; e.g., wire, reg, table) to add the inputs efficiently.
Use only one carrypropagate adder, which you can implement with a
"+" or "–" in verilog.
++
29   ?
in / + / out
 
++
 a) [10 pts] Draw a "dot diagram" for an efficient adder.
 b) [5 pts] Total up and state how much hardware (in area) your
design requires in units of 3:2 adders assuming a 4:2 adder costs
the same as two 3:2 adders and a half adder costs 0.5 3:2 adders.
 c) [5 pts] Estimate the delay of your complete adder by finding
the longest path through your adder and clearly showing that path on
your dot diagram using these estimates:
4:2 delay of 150 ps,
3:2 delay of 100 ps, and
HA delay of 75 ps.
(Delays do not scale with logic complexity to very roughly account
for wire delays.)
 d) [15 pts] Write your design in verilog, test it, and turn in ***.
You may find these as helpful starting points:
prob1.v,
prob1_ref.v,
and
prob1.vt.
Updates:
2017/01/17 Posted.
2017/01/25 Added "*** option 1" to problem 4(b).