Schedule of the Lectures

Schedule of the Labs

Homework Assignments

Week 0: Jan. 5 Course overview

No Labs

Week 1: Jan. 10-12

Reading: Chpt. 1, 2, 3
Course overview, The Process of Design, Digital Hardware Systems: 
- review of logic design, number systems and number representation, arithmetic operations with binary numbers.

Boolean Algebra
- Boolean Algebra, introduction, basic theorems
- Expressions, laws, positive and negative logic.
- Algebraic Simplifications

No Labs

Homework 1: <Solutions>

Chpt.1, Probl: 1.1-1.8 and 1.10-1.12

Week 2: Jan. 19-21 (Friday) <Lecture Notes>

Reading: Chpt. 2,3, 4.1 - 4.6 
Boolean Algebra
- Algebraic Simplifications

Applications of Boolean Algebra:
- Minterm and Maxterm expansions 
- Gate Logic, Implementations

Lab 1:

Introduction to lab instruments and work environment

Homework 2: <Solutions>

Chpt.2, Probl: 2.1-2.5, 2.6(a-b), 2.10(a-c), 2.11(a-c)

Chpt. 3 Probl: 3.13(a-c), 3.14, 3.15(c-e), 3.18, 3.22(a-d), 3.23

Chpt 4 Probl: 4.1, 4.9, 4.25, 4.28-4.29

Week 3: Jan. 24-26 <Lecture Notes>
                                  <Blank K-maps>

Reading: Chpt. 5.1 - 5.4, 5.6 - 5.7, 7.1 - 7.7 
Minimization Tools:
- Karnaugh Maps 
- Multi-level Gate Networks 
- Implementation with NAND and NOR gates

Lab 2:

Introduction to Computer Aided Design: 
Altera design system: tutorial

Homework 3: <Solutions>

Chpt. 5 Probl: 5.3-5.4, 5.6, 5.8, 5.19

Chpt. 7 Probl: 7.1-7.5, 7.14-7.16

Suggested for practice: 5.7, 5.9-5.10, 5.20

Week 4: Jan. 31-Feb.2  <Lecture Notes>

Reading: Chpt. 8, 9.1 - 9.7
Programmable and Non-Gate Logic
- Multiplexers, Decoders 
- ROM and PLA (PAL) 
- Design of combinational networks

Lab 3:

Combinational Network Design using Karnaugh Maps

Homework 4: <Solutions>

Chpt. 8 Probl: 8.A-B, 8.O

Chpt. 9 Probl: 9.1-2, 9.4, 9.8, 9.10, 9.25

Suggested for practice: 8.C-D, 8.N, 9.3, 9.9

Week 5: Feb. 7-9  <Lecture Notes>

Midterm: Feb. 7th

Reading: Chpt. 11,12 
Memory Elements, use of Memory Elements in the design:
- Flip-Flop Circuit: D, R-S, J-K, T 
- Clocking, Edged Triggered, Level Sensitive 
- Master-Slave Latch 
- Timing and Clock Distribution 
- Counters and sequential networks

Lab 4:

Combinational Network Design using Multiplexers and PALs

Homework 5: <Solutions>

Chpt. 11 Probl: 11.1-5, 11.10-11.14

Week 6: Feb. 14-16  <Lecture Notes> <part 2>

Reading: Chpt. 13, 14 
Sequential Logic Design
- Analysis of Clocked Sequential Networks 
- State Graphs and Tables 
- Derivation of State Graphs and Tables 
- Different FF realizations 
- Examples

Lab 5:

Flip--Flops and Latches

Homework 6: <Solutions>

Chpt. 12 Probl: 12.4-5, 12.7-8

Chpt. 13 Probl: 13.2-3, 13.7-8

Chpt. 14 Probl: 14.17, 14.19, 14.23

Suggested for practice: 14.18

Week 7: Feb. (21*)-23   *Holiday
                                           
Reading: Chpt. 15 <Lecture Notes>
<FSM Design Examples>

Sequential Networks Design
- Reduction of State Tables 
- State Assignment 
- Guidelines for State Assignment 
- Practical examples

Lab 6:

Homework 7: <Solutions>

Chpt. 15 Probl: 15.1-4, 15.10-11

Week 8: Feb. 28-March 2

Reading: Chpt. 4.7, 18
Arithmetic Circuits,  <Lecture Notes>
<Lecture on Multipliers>
- Networks for Addition/Subtraction 
- Binary Adders: RCA, CLA 
- Multiplication / Division 
- ALU Design

Lab 7:

Sequential Network Design

Homework 8: <Solutions>

Chpt. 18 Probl: 18.3, 18.9-10

Week 9: March 7-9  

Reading: Chpt. 15, 16.1 - 16.3
Sequential Networks Design
- Reduction of State Tables 
- State Assignment 
- Guidelines for State Assignment 
- Practical examples

Sequential Circuit Design <Lecture Notes>
- Design Examples
- Finite State Machine Design using ROMs and PLAs and PALs 
- Programmable Gate Arrays: PGAs and FPGAs

Lab 8:

Arithmetic Circuits

Homework 9: <Solutions>

Chpt. 16 Probl: 16.1, 16.2, 16.15, 16.16

Week 10: March 14

Reading: Chpt. 1-18
Course Review: Examples, Problems