This course consists of a set of lectures dealing with topics and issues in design of complex and high-performance systems. Those issues range from dynamic and differential logic circuits to contemporary sub-micron circuit techniques.

The lecture starts with a set of papers on advanced circuits and logic. They include fundamental papers on dynamic and differential CMOS circuits which are currently used in high performance processors. The section is followed by a set of papers on differential pass-transistor logic which has been gaining importance in deep sub-micron technology.

The next set of lectures is dedicated to low-power techniques which is becoming a must not only in mobile and portable environment but are equally important issue in high-performance processor design. Recent developments in circuits and logic were presented in this set consisting of papers which are addressing the objective of satisfying low-power requirements. Attention has also been given to the energy-recovery logic.

Next section deals with the system clocking issues, clock distribution techniques and latch design. It contains papers dealing with timing issues in high performance systems such as synchronization, handling of clock skews, design of a fast latch and power saving techniques. Pipelining techniques with the aim of achieving high performance are also addressed.

The section on VLSI algorithms and computer arithmetic shows relationship between implementation techniques, choice of the appropriate algorithm and logic technology. The goal is to extract the benefits of both and achieve efficient and fast implementation. The section contains papers on fast and optimal implementation of ALU, parallel multiplier and MAC units that are a common building block of the Digital Signal Processing (DSP) systems. The presented work emphasizes the importance of appropriate algorithm and its proper mapping into the technology of choice.

1. A. Masaki, "Deep-Submicron CMOS Warms Up to High-Speed Logic", IEEE Circuits and Devices Magazine, November 1992

2. Krambeck, C.M. Lee, H.S. Law, "High-Speed Compact Circuits with CMOS", IEEE Journal of Solid-State Circuits, Vol. SD-13, NO 3, June 1982.

3. V. G. Oklobdzija, R. K. Montoye, "Design-Performance Trade-Offs in CMOS-Domino Logic", IEEE Journal of Solid-State Circuits, Vol. SC-21, NO 2, April 1986.

4. Goncalves, H.J.DeMan, "NORA- A Race free Dynamic CMOS Technique for Pipelined Logic Structures", IEEE Journal of Solid-State Circuits, Vol. SC-18, No 3, June 1983.

5. L.G. Heller, et al, "Cascode Voltage Switch Logic : A Differential CMOS Logic Family", in 1984 Digest of Technical Papers, IEEE International solid-State Circuits Conference, February 1984.

6. L.C.M.G. Pfennings, et al, "Differential Split-Level CMOS Logic for Sub Nanosecond Speeds", IEEE Journal of solid-State circuits, Vol. SC-20, No 5, October 1985.

7. K.M.Chu, D.L. Pulfrey,"A comparison of CMOS Circuit Techniques-Differential Cascode Voltage Switch Logic Versus Conventional Logic", IEEE Journal of solid-State Circuits, Vol. SC-22, No 4, August 1987.

 

1. V. G. Oklobdžija and E. R. Barnes, "On Implementing Addition in VLSI Technology", IEEE Journal of Parallel and Distributed Computing, No. 5, pp. 716-728, 1988.

2. R. F. Sproull, I. E. Sutherland,"Logical Effort: Designing for Speed on the Back of an Envelope",IEEE Advanced Research in VLSI, C. Sequin, ed., MIT Press, 1991.

3. B. S. Amrutur, M. A. Horowitz,"Fast Low-Power Decoders for RAMs",IEEE Journal of Solid-State Circuits, Vol. 36, No. 10, October 2001.

4. P. Rezvani, M. Pedram,"A Fanout Optimization Algorithm Based on the Effort Delay Model",IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, Issue 12, December 2003.

 

8. S. Whitaker, "Pass-Transistor Dual Value Logic for Low-Power CMOS", Electronics, September 1983.

9. K. Yano, et al, "A 3.8-ns CMOS 16*16-b Multiplier using Complementary Pass-Transistor Logic", IEEE Journal of Solid-State Cirruits, Vol.25, No 2, April 1990.

10. K. Yano, et al, "Lean Integration Achieving a Quantum Leap in Performance and Cost of Logic LSIs", Proceeding of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.

11. M. Suzuki, et al, "A 1.5-ns 32-b CMOS ALU in Double Pass-Transistor Logic", Journal of Solid-State Circuits, Vol. 28. No 11, November 1993.

12. N. Ohkubo, et al, "A 4.4-ns CMOS 54*54-b Multiplier using Pass-Transistor Multiplexer", Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.

13. V. G. Oklobdzija and B. Duchene, "Pass-Transistor Dual Value Logic for Low-Power CMOS", Proceedings of the 1995 International Symposium on VLSI Technology, Taipei, Taiwan, May 31-June 2nd, 1995.

14. Dejan Markovic, Borivoje Nikolic, V. G. Oklobdzija, "General Method in Synthesis of Path-Transistor Circuits", Proceedings of the 22st International Conference on Microelectronics (MIEL'2000), Vol. 2, Nis, Serbia, 14-17 May, 2000.

15. F. S. Lai, W. Hwang, "Differential Cascode Voltage Switch with the Pass-Gate (DCVSPG) Logic Tree for High Performance CMOS Digital Systems", Proceedings of the 1993 International Symposium on VLSI Technology, Taipei, Taiwan, June2-4, 1995.

16. A. Parameswar, H. Hara, T. Sakurai, "A Swing Restored Pass-Transistor Logic-Based Multiply and Accumulate Circuit for Multimedia Applications", Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May -4, 1994.

17. T. Fuse, et al, "0.5 V SOI CMOS Pass-Gate Logic", Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco February 8, 1996.

18. V. G. Oklobdzija, "Differencial and Pass-Transistor CMOS Logic for High-Performance Systems", Proceeding of the 21st International Conference on Microelectronics(MIEL'97), Vol. 2, Nis, Yugoslavia, 14-17 September , 1997.

1. A. Chandrakasan, R. Brodersen, "Minimizing Power Consumption in CMOS Circuits", IEEE Proceedings 1995.

2. T. Kuroda and T. Sakurai "Overview of Low-Power ULSI Circuit Techniques", IEICE Trans. Electronics, E78-C, No. 4, April 1995, pp.334-344, INVITED PAPER, Special Issue on Low-Voltage Low-Power Integrated Circuits.

3. Y. Sasaki, et al, "Multi-Level Pass-Transistor Logic for Low-Power ULSIs", Proceedings of the 1995 Low-Power Integrated Circuits.

4. E. De Man, M. Schobinger, "Power dissipation in the Clock System of highly pipelined ULSI CMOS Circuits", Proceedings of the International Workshop on Low-Power Design, 1994.

5. C. Nagendra, et al, "A Comparison of the Power-Delay Characteristics of CMOS Adders", Proceedings of the International Workshop on Low-Power Design, 1994.

6. C. Tan, et al, "Minimization of Power in VLSI Circuits Using Transistor Sizing, Input Ordering, and Statistical Power Estimation", Proceedings of the International Workshop on Low-Power Design, 1994.

7. M. Horowitz, et al, "Low-Power Digital Design", Proceedings of the 1994 IEEE Symposium on Low-Power Electronics, 1994.

8. H. Kojima, et al, "Power Analysis of a Programmable DSP for Architecture/Program Optimization", Proceedings of the 1995 Low-Power Symposium.

9. V. G. Oklobdzija, Dragan Maksimovic, Fengcheng Lin, "Pass-Transistor Adiabatic Logic Using Sing Power-Clock Supply", Circuits and Systems II, Analog and Digital Signal Processing, IEEE Transaction on, Vol. 44, Issue. 10, Oct. 1997.

10. V. G. Oklobdzija, “Architectural Tradeoffs for Low Power”, International Symposium on Computer Architecture, Barcelona, SPAIN, June 27-July 1^st, 1998.

11. David M. Brooks, et. al, “Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors”, IEEE Micro, Nov/Dec 2000.

12. Victor Zyuban, “Optimization of Scannable Latches for Low Energy”, IEEE Transactions on VLSI Systems, Vol. 11, No. 5, October 2003.

13. Victor Zyuban, et. al, “Integrated Analysis of Power and Performance for Pipelined Microprocessors”, IEEE Transactions on Computers, Vol. 53, No. 8, August 2004.

 

1. Eby G. Friedman, "Clock Distribution Networks in VLSI Circuits and Systems", in IEEE Press, 1995.

2. Wagner, "Clock System Design", IEEE Design & Test of Computers, October 1988.

3. S. H. Unger, C. Tan, "Clocking Schemes for High-Speed Digital Systems", IEEE Transactions on Computers, Vol C-35, No 10, October 1986.

4. V. Stojanovic, Oklobdzija V. G.,"Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems", IEEE Journal of Solid-State Circuits, Vol. 34, No. 4, April 1999.

5. Minami, M. Takano, "Clock Tree Synthesis Based on RC Delay Balancing", Proceedings IEEE Custom Integrated Circuits Conference, p. 28.3.1-8.3.4, may 1992.

6. Kojima, S. Tanaka, K. Sasaki, "Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry", IEEE Journal of Solid-State Circuits, Vol.30, No.4, April 1995.

7. M. Afghahi, C. Svensson, "A Unified Single-Phase Clocking Scheme for VLSI Systems", IEEE Journal of Solid-State Circuits, Vol 25, No 1, February 1990.

8. H. Partovi et al, "Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements", Proceeddings of 1996 IEEE International Solid-State Circuits Conference, San Francisco, California February 1996.

9. D. Dobberpuhl et al, "A 200MHz 64-b Dual-Issue CMOS Microprocessor", IEEE journal of Solid-State Circuits, Vol 27, No 11, November 1992.

10. B. J. Benschneider, et al, "A 300-MHz 64-b Quad-Issue CMOS RISC Microprocessor", IEEE Journal of Solid-State Circuits, Vol 30, No 11, November 1995.

11. Nikola Nedovic, Vojin G. Oklobdzija, William W. Walker, "A Clock Skew Absorbing Flip-Flop", IEEE International Solid-State circuits Conference, February 12, 2003.

12. Vojin G. Oklobdzija , "Issues in System on the Chip Clocking", Invited Paper, Proceedings of the IEEK System on Chip Design Conference, Seoul, Korea, November 5-6, 2003.

13. V. G. Oklobdzija,"Clocking and Clocked Storage Elements in a Multi-Gigahertz Environment", IBM, J. RES. & DEV. Vol. 47, No. 5/6, September/November 2003

1. Weinberger, J. L. Smith,"A Logic for High-Speed Addition", National Bureau of Standards, Circulation 591, p.3-12, 1958.

2. Naini, D. Bearden, W. Anderson, "A 4.5nS 96-b CMOS Adder Design", IEEE 1992 Custom Integrated Circuits Conference, 1992.

3. Sklanski, "Conditional-Sum Addition Logic", IRE Transaction on Electronic Computers, EC-9,pp.26-231, 1960.

5. V. G. Oklobdzija, E. R. Barnes, "Some Optimal Schemes for ALU Implementation in VLSI Technology", Proceedings of 7th Symposium on Computer Arithmetic, June 4-6, 1985, University of Illinois, Urbana, Illinois. 

6. B. D. Lee, V. G. Oklobdzija, "Improved CLA Scheme with Optimized Delay", Journal of VLSI Signal Processing, Vol.3, p.265-274, 1991.

7. V. G. Oklobdzija, Bart R. Zeydel, Hoang Dao, Sanu Mathew, Ram Krishnamurthy, "Energy-Delay Estimation Technique for High-Performance Microprocessor", Proceesing of the Symposium on Computer Arithmetic , 1063-6899, 2003.

8. Sanu Mathew, Mark Anders, Ram K. Krishnamurthy, Shekhar Borkar, "A 4-GHz 130-nm Address Generation Unit With 32-bit Sparse-Tree Adder Core", IEEE Journal of Solid-State circuits, Vol38, No.5, May 2003.

9. V. G. Oklobdzija, "An Algorithmic and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis", IEEE Transactions on VLSI Systems, Vol.2, No.1, March 1994.

10. C. S. Wallace, "A Suggestion for a Fast Multipliers", IEEE Transactions on Electronic Computers, EC-13, p.14-17, 1964.

11. L. Dadda, "Some Schemes for Parallel Multipliers", Alta Frequenza, Vol.34, p.349-356, March 1965.

12. W. J. Stenzel, W. J. Kubitz, "A Compact High-Speed Parallel Multiplication Scheme", IEEE Transaction on Computers, C-26, p.948-957, 1977.

13. V. G. Oklobdzija, D. Villeger, S. S. Liu, "A method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers using and Algorithmic Approach", IEEE Transaction on Computers, Vol.45, No.3, march 1996.

14. V. Oklobdzija, "High-Speed VLSI Arithmetic Units: Adders and Multipliers", in "Design of High-Performance Microprocessor Circuits", Book Chapter, Book edited by A. Chandrakasan, IEEE Press, 2000.