Department of Electrical and Computer Engineering


Digital Integrated Circuits: Spring 2003



Prof. Vojin G. Oklobdzija

Office: Engineering II, Room 3007

Office Hours: 10-11 Tu-Th, Room 3007, e-mail appointment preferred (please see the appointment policy)


Times and Location


9:00-9:50 Tu-Th, 106 Wellman


Teaching Assistants:


Name Hoang Dao Chi Ho Law
Office Hours 1:30-2:30 Tuesday 3:30-4:30 Tuesday
Office Location TB207-120 EUII-2155



Course Information

Lab Information



Downloading Acrobat Reader


Midterm: May 1st, 2003, same classrooom, same time (9-10am).


Course Information

Course Outline

Course Overview, Reading Assignments, and Homework Assignments


Related Courses: 

UC Berkeley: 

EECS 141: Digital Integrated Circuits (Prof. J. Rabaey)

Stanford University

EE 313: Digital MOS Integrated Circuits (Prof. Horowitz)

EE 371: Advanced VLSI Circuits Design (Prof. Horowitz)

Related Links: 


A very useful link showing simulation of various digital components. Courtesy of Prof. Alain Guyot, TIMA, Grenoble, FRANCE. Please use it and report any errors in English to me or Prof. Alain Guyot directly. From TIMA and



Midterm and Solution

Quizzes and Solutions

Lab quizzes and lab report grade

Online Grade Posting 

Posted by last four digits of Student ID Number

Lab Report Scores

Quiz Scores

Homework Scores

Midterm Scores

Lab Information

Laboratory Guidelines

Lab Report Guidelines

Lab Report Coversheet






TEXTBOOK:  Neil Weste and Kamran Eshraghian: Principles of CMOS VLSI Design - A Systems Perspective, 2nd Ed., Addison Wesley, 1993.

Schedule of the Lectures

Schedule of the Labs

Homework Assignments

Week 1: April 1,  3

Reading: Chpt. 1 
Introduction to CMOS Circuits

No Labs

Homework 1: (due 8th) Solution

1.1-1.6  (Fig. 1.11 = 1.12 in the new book, probl. 1.6)

Week 2: April 8,  10 

Reading: Chpt. 2 
MOS Transistor Theory

Lab 1: Magic Tutorial


Homework 2: (due 15th) Solution


Week 3: April 15,  17

Reading: Chpt. 3 
CMOS Processing Technology

Lab 2: MOS Parameters


Homework 3: (due 22nd) Solution

Sect. 3.8: 1, 3-7

Week 4: April 22,  24

Reading: Chpt. 4 
Circuit Characterization and Performance Estimation

Lab 3: CMOS Inverter and Gates


Homework 4: (due 29th)

Sect. 4.15: 3-5, 7, 10-11

Week 5: April 29,  May 1st

Reading: Chpt. 5
CMOS Circuits and Logic Design

Lab 4: Master-Slave Latch


Homework 5: (due May 6th)

Sect. 5.9: 1-3, 5

Week 6: May 6,  8

Reading: Chpt. 5 
CMOS Circuits and Logic Design

Lab 5: CMOS Domino Circuits


Homework 6: (due May 13th)

Sect. 5.9: 7-9, 12, 14

Week 7: May 13,  15

Reading: Logical Effort Handouts 
Logical Effort Theory

Final Project: Functional Verification

Homework 7:

Week 8: May 20,  22

Reading: Chpt. 8 

CMOS Subsystem Design

Final Project: Circuit Sizing

Homework 8:

Week 9: May 27,  29 

Reading: handouts 
Arithemtic Circuits cont.

Final Project: HSPICE Simulation

Homework 9:

Week 10: June 3,  5  

Reading: All Chpt. 
Course Review

Final Project: Layout

Homework 10:



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(Page last modified:04/24/2003  Wednesday, 20-Apr-2005 15:51:59 PDT)