People of the VCL

Faculty
	Professor Bevan Baas
Graduate students
	Dean Truong Ph.D. Candidate Power grid integrity DVFS algorithm implementation Multi-Vdd design flow		Zhibin Xiao Ph.D. Candidate Architectures Video and multimedia applications Memory system design
	Anh Tran Ph.D. Candidate On-chip interconnects Multi-core architectures VLSI DSP implementation		Bin Liu Ph.D. Candidate DVFS circuits and algorithms Processor architecture AES encryption
	Aaron Stillmaker Ph.D. Student Processor architecture Database record processing Algorithm mapping		Jon Pimentel Ph.D. Student SAR image processing Processor architecture Biomedical imaging
	Jeremy Webb Ph.D. Student High-speed board design Many-core VLSI System interfacing		Brent Bohnenstiehl Ph.D. Student Processor architectures LTE baseband processing VLSI Design
	Emmanuel Adeagbo Ph.D. Student Circuit design VLSI Design Many-core tools
	Houshmand Shirani Mehr MS Student Low Density Parity Check (LDPC) Decoders LDPC Algorithms Digital signal processing hardware		Michael Braly MS Student Many-core processor tools Processor architectures DSP applications
	Samir Kagadkar MS Student VLSI design Processor architectures Digital circuits		Nima Mostafavi MS Student Hardware design DSP applications Software tools
	Christine Watnik MS Student Viterbi accelerator AsAP code scheduler DSP C compiler backend
Undergraduate Researchers
	Victoria Harvey Many-core simulation Application development
Alumni
	Prof. Zhiyi Yu Ph.D. ECE, Oct. 2007 Associate Professor Fudan University Network on chip GALS clocking AsAP 1.0 physical design		Prof. Tinoosh Mohsenin Ph.D. ECE, Nov. 2010 Assistant Professor University of Maryland, Baltimore County LDPC algorithms LDPC architectures and processor design Many-core processor arrays
	Ryan Apperson MS ECE, Sept. 2004 Senior Electrical Engineer Physio-Control R&D Asynchronous data interfacing circuits SRAM design Full-custom CMOS layout		Omar Sattari MS ECE, Sept. 2004 Software Engineer     CornerTurn Instructor     Allied American University Address generation and branching Programming assembler, config FFT algorithm mapping
	Mike Lai MS ECE, Sept. 2004 Design Engineer Altera High-speed pipelined signed multiplier High-speed modular signed adder Full-custom CMOS layout		Mike Meeuwsen MS ECE, April 2005 Hardware Engineer Intel, Digital Enterprise Group 802.11a algorithm mapping Architectural enhancements Instruction set design
	Toney Jacobson MS ECE, July 2007 Patent Associate Fenwick & West LLP Fast Fourier Transform (FFT) architectures Digital system design High-speed FPGA design		Eric Work MS ECE, Sept. 2007 Software Engineer S-Machines Arbitrary task to 2D mesh mapping Software tool flow CAD tools
	Wayne Cheng MS ECE, January 2008 ASIC Design Engineer Uniquify Dynamic voltage supply circuits Dynamic voltage and frequency circuits Transistor-level power simulations		Gouri Landge MS ECE, December 2009 Intel, Digital Home Group Video motion estimation architectures VLSI 65 nm motion estimation accelerator Programmable video processing hardware
	Stephen Le MS ECE, March 2010 Component Design Engineer Architecture Simulation Intel, Visual Computing Group Parallel H.264 application development High-speed parallel simulator Tool integration		Lucas Stillmaker MS ECE, September 2011 Graphics Hardware Engineer Intel, Visual and Parallel Computing Group (VPG) Intel Architecture Group (IAG) Parallel application development Parallel database sorting algorithms Digital system design
	Trevin Murakami MS ECE, December 2011 Product Engineer Intel, NAND Solutions Group (NSG) Many-core simulator Processor architectures Digital signal processing hardware
Undergraduate Researchers
William Au Yeung,   BS ECE, June 2005 Tomoko Tsuruta,   BS ECE, June 2005 Jason Cheung,   BS CS, June 2005 Leo Chan,   BS ECE, June 2006 Bassem Saad,   BS ECE, June 2006 Daniel Gurman,   BS ECE, June 2006 Sam Lee,   BS ECE, June 2006 Chi Chen,   BS ECE, June 2006 Kyle Piper,   BS ECE, June 2007
	Henna Huang BS ECE, June 2009 Ph.D. Student MIT Parallel H.264 application development Multi-processor characterization Tool development		Gary Chung BS ECE, August 2009 Apple Computer Embedded processor code development File system design and implementation Config design of 334-processor system
	Brian Zimmer BS ECE, June 2010 Ph.D. Student UC Berkeley MP3 decoder reference design MP3 decoder implementation		Layne Miao BS ECE, June 2011 Analog Design Engineer Intel Corporation AsAP2 board bring up System characterization

Current Research

Asynchronous Array of simple Processors (AsAP)

Many members of the VCL are participating in work on the circuits, functional units, architecture, interconnection network, algorithms, and applications for a high-performance and energy-efficient processing system targeting computationally-demanding multi-algorithm DSP system applications. The single-chip processing system is comprised of a large number of fine-grain asynchronously-operating programmable processors connected by a reconfigurable 2-dimensional mesh network.

AsAP 1.  The 0.18 μm AsAP 1 chip contains 36 programmable processors, operates at over 610 MHz at 2.0 V, and is believed to be the second highest clock rate processor designed in any university. Details of the chip were presented in the Technology and Architecture Directions session at ISSCC in Feb. 2006. See the paper below.

Also see the EE Times article "Asynchronous array of processors chip presented at ISSCC 2006," February 9, 2006.

AsAP 2.  A second generation 65 nm CMOS design contains 167 processors with dedicated FFT, Viterbi, and video motion estimation processors; 16 KB shared memories; and long-distance inter-processor interconnect. The programmable processors can individually and dynamically change their supply voltage and clock frequency. The chip is fully-functional. Processors operate up to 1.2 GHz at 1.3 V which is believed to be the highest clock rate fabricated processor designed in any university. At 1.2 V, they operate at 1.07 GHz and 47 mW when 100% active. At 0.675 V, they operate at 66 MHz and 608 μW when 100% active. This operating point enables 1 trillion MAC or ALU ops/sec with a power dissipation of only 9.2 Watts. Due to its MIMD architecture and fine-grain clock oscillator stalling, this energy efficiency per operation is almost perfectly constant across widely varying workloads--which is not the case for many architectures.

Low Density Parity Check (LDPC) Decoders

We are working on LDPC algorithms, architectures, and circuits targeting several regimes, with a continual emphasis on high energy efficiency:
• Very high rate decoders
• Efficient decoding algorithms useful at many throughput rates

Special Purpose Processors

We are working on algorithms, architectures, and circuits for a number of dedicated purpose processing engines. Several active projects include:
• Fast Fourier Transform (FFT)
• Viterbi decoder
• H.264 video encoding and decoding
• other accelerator architectures



Sponsors of Our Work

	National Science Foundation   • CAREER award No. 0546907   • CCF Grant No. 0430090   • CCF Grant No. 0903549   • CCF Grant No. 1018972   • REU Grant 2005   • REU Grant 2010		SRC, Semiconductor Research Corporation   • GRC Grant 1598.001   • CSR Grant 1659.001   • GRC Grant 1971.001
	UC MICRO		ST Microelectronics
	C2S2   • Grant 2047.002.014		Intellasys Corporation
	Intel Corporation	SEM	SEM
	Committee on Research, Faculty Research Grant		Fudan University
	Xilinx Incorporated, Equipment grants		Atheros Communications, Equipment grant
We also acknowledge support from:   • Artisan   • MOSIS
Any opinions, findings and conclusions or recomendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation (NSF).
The authors acknowledge the support of the C2S2 Focus Center, one of six research centers funded under the Focus Center Research Program (FCRP), a Semiconductor Research Corporation entity.

Miscellaneous

Computing resources within the VLSI Computation Lab

Publications

Publications in review are provided to sponsors but not yet listed here.

2012


• Zhibin Xiao and Bevan Baas,
  " Processor Shapes and Topologies for Dense On-chip Networks,"
  presented in the IEEE International Solid-Sate Circuit Conference (ISSCC 2012) student forum, San Francisco, CA, Feb. 2012.
  

  2011
  

• Bin Liu and Bevan Baas,
  "Parallel AES Encryption Engines for Many-Core Processor Arrays,"
  To appear in the IEEE Transactions on Computers".

• Aaron Stillmaker, Zhibin Xiao and Bevan M. Baas,
  "Toward More Accurate Scaling Estimates of CMOS Circuits from 180 nm to 22 nm,"
  Technical Report ECE-VCL-2011-4, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2011.

• Trevin Murakami,
  "A SystemC Single-Cycle Simulator,"
  Masters Thesis, Technical Report ECE-VCL-2011-3, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2011.

• Bin Liu and Bevan Baas,
  "A High-Performance Area-Efficient AES Cipher on a Many-Core Platform,"
  IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC), Pacific Grove, CA, November 2011.
  Nominated for Best Student Paper.

• Houshmand Shirani-Mehr, Tinoosh Mohsenin and Bevan Baas,
  "A Reduced Routing Network Architecture for Partial Parallel LDPC Decoders,"
  IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC), Pacific Grove, CA, November 2011.
  

• Zhibin Xiao, Stephen Le and Bevan Baas,
  "A Fine-Grained Parallel Implementation of a H.264/AVC Encoder on a 167-processor Computational Platform,"
  IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC), Pacific Grove, CA, November 2011.
  

• Anh Tran and Bevan Baas,
  "RoShaQ: High-Performance On-Chip Router with Shared Queues,"
  IEEE International Conference on Computer Design (ICCD), Amherst, MA, October 2011, pp. 232-238.
  Best Paper Award.

• Lucas Stillmaker,
  "SAISort: An Energy Efficient Sorting Algorithm Many-Core Systems,"
  Masters Thesis, Technical Report ECE-VCL-2011-2, VLSI Computation Laboratory, ECE Department, University of California, Davis, September 2011.

• Anh Tran and Bevan Baas,
  "Design of Bufferless On-Chip Routers Providing In-Order Packet Delivery,"
  SRC Technology and Talent for the 21st Century (TECHCON), Austin, TX, USA, Sep. 2011, S14.3.

• Zhibin Xiao and Bevan Baas,
  "A 1080p H.264/AVC Baseline Residual Encoder for a Fine-grained Many-core System,"
  IEEE Transactions on Circuits and Systems for Video Technology, vol. 21, no. 7, pp. 890-902, July 2011.
  

• Bevan M. Baas,
  "A case for fine-grained many-core processor arrays,"
  Parallel Algorithms, Programming, Architectures Workshop at the 48th ACM/IEEE Design Automation Conference (DAC), San Diego, CA, June 5, 2011.
  Invited.

• Tinoosh Mohsenin, Houshmand Shirani-Mehr and Bevan Baas,
  "Low Power LDPC Decoder with Efficient Stopping Scheme for Undecodable Blocks,"
  In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'11), May 2011.
  Invited.

• Jeremy W. Webb,
  "A High Performance Baseband Instrument,"
  Masters Thesis, Technical Report ECE-VCL-2011-1, VLSI Computation Laboratory, ECE Department, University of California, Davis, March 2011.

  2010
  

• Tinoosh Mohsenin,
  "Algorithms and Architectures for Efficient Low Density Parity Check (LDPC) Decoder Hardware,"
  Ph.D Dissertation, Technical Report ECE-VCL-2010-4, VLSI Computation Laboratory, ECE Department, University of California, Davis, November 2010.

• Dean Truong and Bevan Baas,
  "Massively Parallel Processor Array for Mid-/Back-end Ultrasound Signal Processing,"
  In Proceedings of the IEEE Biomedical Circuits and Systems Conference (BioCAS), Paphos, Cyprus, Nov. 2010, pp. 274-277.
  Nominated for Best Student Paper.

• Anh Tran and Bevan Baas,
  "DLABS: a Dual-Lane Buffer-Sharing Router Architecture for Networks on Chip,"
  In Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS), Cupertino, CA, Oct. 2010, pp. 331-336.
  

• Zhibin Xiao, Stephen Le and Bevan Baas,
  "An Energy-Efficient Parallel H.264/AVC Baseline Encoder on a Fine-grained Many-core System,"
  Technology and Talent for the 21st Century (TECHCON 2010), Austin, TX, Sep. 2010.
  

• Anh Tran and Bevan Baas
  Design of an Energy-Efficient 32-bit Adder Operating at Subthreshold Voltages in 45-nm CMOS",
  International Conference on Communications and Electronics (ICCE), Aug. 2010, pp. 87-91.
  

• Anh Tran, Dean Truong and Bevan Baas,
  "A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms,"
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, no. 6, pp. 897-910, June 2010.
  Invited.

• Dean Truong and Bevan Baas,
  "Circuit Modeling for Practical Many-core Architecture Design Exploration,"
  In Proceedings of the 47th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, June 13-18, 2010, pp. 627-628.
  Wild And Crazy Ideas (WACI) Session.
  "WACIest" Best-In-Session Paper.

• Tinoosh Mohsenin, Dean Truong and Bevan Baas,
  "A Low-Complexity Message Passing Algorithm for Reduced Routing Congestion in LDPC Decoders,"
  IEEE Transactions of Circuits and Systems I (TCAS-I), vol. 57, no. 5, pp. 1048-1061, May 2010.
  Invited.

• Zhiyi Yu and Bevan Baas,
  "A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors,"
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 18, no. 5, pp. 750-762, May 2010.

• Stephen Le,
  "A Fine Grained Many-Core H.264 Video Encoder,"
  Masters Thesis, Technical Report ECE-VCL-2010-3, VLSI Computation Laboratory, ECE Department, University of California, Davis, March, 2010.

• Tinoosh Mohsenin and Bevan Baas,
  "A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders,"
  Journal of Signal Processing Systems for Signal, Image, and Video Technology, available online, Feb. 2010.

  2009
  

• Gouri Landge,
  "A Configurable Motion Estimation Accelerator For Video Compression,"
  Masters Thesis, Technical Report ECE-VCL-2009-4, VLSI Computation Laboratory, ECE Department, University of California, Davis, December, 2009.

• Tinoosh Mohsenin and Bevan Baas,
  "Trends and Challenges in LDPC Hardware Decoders,"
  In Proceedings of the IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC), November 2009, pp. 1273-1277.
  Invited.

• Tinoosh Mohsenin and Bevan Baas,
  "High Throughput and Energy Efficient LDPC Decoders using Multi-Split-Row Threshold Method,"
  TECHCON 2009, Sept. 2009.

• Tinoosh Mohsenin, Dean Truong and Bevan Baas,
  "An Improved Split-Row Thresholding Decoding Algorithm for LDPC Codes,"
  In Proceedings of the IEEE International Conference on Communications (ICC'09), June 2009.

• Tinoosh Mohsenin, Dean Truong and Bevan Baas,
  "Multi-Split-Row Threshold Decoding Implementations for LDPC Codes,"
  In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'09), May 2009, pp. 2449-2452.

• Anh Tran, Dean Truong and Bevan Baas,
  "A Low Cost High-Speed Source-Synchronous Interconnection Technique for GALS Chip Multiprocessors,"
  In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'09), May 2009, pp. 996-999.

• Anthony Jacobson, Dean Truong and Bevan Baas,
  "The Design of a Reconfigurable Continuous-Flow Mixed-Radix FFT Processor,"
  In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'09), May 2009, pp. 1133-1136.

• Anh Tran, Dean Truong and Bevan Baas,
  "A GALS Many-Core Heterogeneous DSP Platform with Source-Synchronous On-Chip Interconnection Network,"
  In Proceedings of the ACM/IEEE International Symposium on Networks on Chip (NOCS) , May 2009, pp. 214-223.

• Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Anthony Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Anh Tran, Zhibin Xiao, Eric Work, Jeremy Webb, Paul Mejia, Bevan Baas,
  "A 167-Processor Computational Platform in 65 nm CMOS,"
  IEEE Journal of Solid-State Circuits (JSSC), vol. 44, no. 4, pp. 1130-1144, April 2009.
  Invited.

• Zhiyi Yu and Bevan Baas,
  High Performance and Energy Efficient Many-Core DSP Systems,
  VDM Publishing House Ltd., 2009. Available at amazon.com.
  Invited.

• Zhiyi Yu and Bevan Baas,
  "High Performance, Energy Efficiency, and Scalability with GALS Chip Multiprocessors,"
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 17, no. 1, pp. 66-79, Jan. 2009.

  2008
  

• Tinoosh Mohsenin, Pascal Urard and Bevan Baas,
  "A Thresholding Algorithm for Improved Split-Row Decoding of LDPC Codes,"
  In Proceedings of the IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC), October 2008, MA8b1-8.

• Anh Tran, Dean Truong and Bevan Baas,
  "A Complete Real-Time 802.11a Baseband Receiver Implemented on an Array of Programmable Processors,"
  In Proceedings of the IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC), October 2008, pp. 165-170.

• Zhibin Xiao and Bevan Baas,
  "A High-Performance Parallel CAVLC Encoder on a Fine-Grained Many-core System,"
  In Proceedings of the IEEE International Conference on Computer Design (ICCD '08), October 2008, pp. 248-254.

• Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan Baas,
  "A 167-processor Computational Array for Highly-Efficient DSP and Embedded Application Processing,"
  In Proceedings of the IEEE HotChips Symposium on High-Performance Chips, (HotChips 2008), August 2008.

• Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan Baas,
  "A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling,"
  In Proceedings of the Symposium on VLSI Circuits, June 2008, C3.1., pp. 22-23.

• Zhiyi Yu and Bevan Baas,
  "A Low-Area Interconnect Architecture for Chip Multiprocessors,"
  In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2008, pp. 2857-2860.

• Wayne Cheng and Bevan Baas,
  "Dynamic Voltage and Frequency Scaling Circuits with Two Supply Voltages,"
  In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2008, pp. 1236-1239.

• Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Tinoosh Mohsenin, Bevan Baas,
  "Architecture and Evaluation of an Asynchronous Array of Simple Processors,"
  Journal of VLSI Signal Processing Systems, March 2008.

• Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Dean Truong, Tinoosh Mohsenin, Bevan Baas,
  "AsAP: An Asynchronous Array of Simple Processors,"
  IEEE Journal of Solid-State Circuits (JSSC), vol. 43, no. 3, pp. 695-705, March 2008.

• Tinoosh Mohsenin and Bevan Baas,
  "An 18 Gbps 2048-bit 10GBASE-T Ethernet LDPC Decoder,"
  IEEE International Solid-State Circuits Conference (ISSCC) 2008 Student Forum, February 2008.

• Wayne H. Cheng,
  "Approaches and Designs of Dynamic Voltage and Frequency Scaling,"
  Masters Thesis, Technical Report ECE-CE-2008-1, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2008.

  2007
  

• Zhiyi Yu,
  "High Performance and Energy Efficient Multi-core Systems for DSP Applications,"
  Ph.D Dissertation, Technical Report ECE-CE-2007-5, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2007.

• Ryan Apperson, Zhiyi Yu, Michael Meeuwsen, Tinoosh Mohsenin, Bevan Baas,
  "A Scalable Dual-Clock FIFO for Data Transfers between Arbitrary and Haltable Clock Domains,"
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 15, no. 10, pp. 1125-1134, October 2007.

• Eric W. Work,
  "Algorithms and Software Tools for Mapping Arbitrarily Connected Tasks onto an Asynchronous Array of Simple Processors,"
  Masters Thesis, Technical Report ECE-CE-2007-4, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2007.

• Anthony T. Jacobson,
  "A Continuous-Flow Mixed-Radix Dynamically-Configurable FFT Processor,"
  Masters Thesis, Technical Report ECE-CE-2007-3, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2007.

• Michael Meeuwsen, Zhiyi Yu, and Bevan Baas,
  "A Shared Memory Module for Asynchronous Arrays of Processors,"
  EURASIP Journal on Embedded Systems, vol. 2007, Article ID 86273, 13 pages, 2007.

• Bevan Baas, Zhiyi Yu, Michael Meeuwsen, Omar Sattari, Ryan Apperson, Eric Work, Jeremy Webb, Michael Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung,
  "AsAP: A Fine-grain Multi-core Platform for DSP Applications,"
  IEEE Micro, Volume 27, Number 2, March/April 2007.
  Invited.

• Tinoosh Mohsenin and Bevan M. Baas,
  "High-Throughput LDPC Decoders Using A Multiple Split-Row Method,"
  In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '07), April 2007.

  2006
  

• Zhiyi Yu and Bevan M. Baas,
  "Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles ,"
  In Proceedings of the IEEE International Conference on Computer Design (ICCD '06), October 2006, pp. 174-179.

• Tinoosh Mohsenin and Bevan M. Baas,
  "Split-row: A reduced complexity, high throughput LDPC decoder architecture ,"
  In Proceedings of the IEEE International Conference on Computer Design (ICCD '06), October 2006, pp. 320-325.

• Bevan Baas, Zhiyi Yu, Michael Meeuwsen, Omar Sattari, Ryan Apperson, Eric Work, Jeremy Webb, Michael Lai, Daniel Gurman, Chi Chen, Jason Cheung, Dean Truong, Tinoosh Mohsenin,
  "Hardware and Applications of AsAP: An Asynchronous Array of Simple Processors,"
  In Proceedings of the IEEE HotChips Symposium on High-Performance Chips, (HotChips 2006), August 2006.

• Zhiyi Yu and Bevan M. Baas,
  "Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems,"
  In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI '06), March 2006, pp. 378-384.

• Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Tinoosh Mohsenin, Mandeep Singh, Bevan M. Baas,
  "An Asynchronous Array of Simple Processors for DSP Applications,"
  In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC '06), February 2006, pp. 428-429, 663.

  2005 and prior
  

• Michael J. Meeuwsen,
  "A Shared Memory Module for an Asynchronous Array of Simple Processors,"
  Masters Thesis, Technical Report ECE-CE-2005-2, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2005.

• Bevan M. Baas,
  "A Generalized Cached-FFT Algorithm,"
  In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2005, March 2005, pp. V-89-92.

• Michael J. Meeuwsen, Omar Sattari, and Bevan M. Baas,
  "A Full-Rate Software Implementation of an IEEE 802.11a Compliant Digital Baseband Transmitter,"
  In Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS '04), Oct. 2004.

• Ryan W. Apperson,
  "A Dual-Clock FIFO for the Reliable Transfer of High-Throughput Data Between Unrelated Clock Domains,"
  Masters Thesis, Technical Report ECE-CE-2004-5, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2004.

• Michael A. Lai,
  "Arithmetic Units for a High Performance Digital Signal Processor,"
  Masters Thesis, Technical Report ECE-CE-2004-6, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2004.

• Omar Sattari,
  "Fast Fourier Transforms on a Distributed Digital Signal Processor,"
  Masters Thesis, Technical Report ECE-CE-2004-7, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2004.

• Bevan M. Baas,
  "A Parallel Programmable Energy-Efficient Architecture For Computationally-Intensive DSP Systems,"
  In Proceedings of the IEEE Asilomar Conference on Signals, Systems and Computers, 37th, November 2003.

• Howard CheHao Chang and Bevan M. Baas,
  "Mapping an FIR Filter to a 2-Dimensional Mesh of Processors,"
  Technical Report ECE-CE-2003-1, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2003.

• New 167-processor chip is super-fast, ultra energy-efficient
  • EurekAlert news service operated by AAAS
  • TechRadar
  • UC Davis News Service

• Arbitrary graph mapping algorithms and tools
• Dynamic supply voltage and clock frequency circuits and algorithms
• Programmable DSP processor design
• Parallel DSP algorithms
• Reconfigurable inter-processor networks for various network traffic styles
• Functional unit and circuit design
• Processor simulation, emulation, and CAD design flow
• Shorter-term projects (possibly for undergraduate students)
  • Enhancements to our C compiler
  • Measurement and characterization of our multi-core chips (longer term)
  • Writing various FFTs on AsAP array
  • Chip design CAD tool projects
• A note to interested prospective students

Downloadable Tools Developed in the VCL

• Arbitrary Graph to 2D Mesh Mapping Tool    
  
  
• Low overhead parallel-task linux based simulator    
  
  
• Dual-clock FIFO    
  
  

VCL-Specific Material

• Directions to the VCL lab
• Some VCL Guidelines for students in the VCL lab (good computer etiquette, writing papers, responding to reviewers)
• VLSI & Sig. Processing conferences, Micro Sys News Calendar
• Unix command notes, Unix tutorials, latex notes
• Information on the FPGA boards used in the lab
• Getting started in the VCL lab

Other CAD Tools We Use

• Some tools installed locally
• Cadence
  • Tool notes
  • NC verilog
  • SoC Encounter
  • Virtuoso
• Synopsys
  • Design Compiler
  • HSpice
  • NanoSim
• Mentor Graphics
  • Calibre
  • Expedition
• Magic layout tool
  • Magic web site
• Tutorial web pages
  • Cadence, NCSU, and various tutorials

Other Useful Links

• IEEE papers
  • JSSC
  • TVLSI
  • TCAS I: Regular papers;
  Publication statistics
  • TCAS II: Express briefs
• Microprocessors through the ages
• Intl. Tech. Roadmap for Semiconductors (ITRS)
• MOSIS web site
• Future technology spice decks from UCB's Predictive Technology Model
• Accurel for FIBing, packaging,...
• AsAP Wikipedia page
• gds2pov, a 3D GDSII visualization tool

Informative References

• LaTeX: Formulas,
• Deep chip's CAD tool review from CAD '04

A few group pictures

Aaron, Michael, Emmanuel, Jon, Ahn, Samir, Zhibin, Brent, and Bin in the office-lab; April 4, 2012.

Group dinner celebrating Jeremy, Lucas, and Trevin's graduations as well as Ahn's best paper award and Bin's best paper nomination; January 25, 2012.

Group lunch celebrating end of Spring quarter; June 10, 2009.

Dean and Anh in office-lab; January 25, 2009.

Dean, Zhibin and Paul in office-lab; March 27, 2008.

Zhibin, Dean, Anh, Tinoosh, and Paul working on AsAP2 bringup; October 12, 2007.

Tinoosh, Dean, and Zhibin working on AsAP2 bringup; October 11, 2007.

Dean, Zhibin, Anh, Tinoosh, Paul, and Bevan at ECE Grad Student BBQ in Kemper courtyard; October 4, 2007.

Toney, Wayne, Zhibin, Anh, Zhiyi, Tinoosh, Paul, Dean, and Bevan celebrating Toney's and Wayne's graduations at Woodstock's; August 29, 2007.

Tinoosh, Dean, Christine, Wayne, and Zhiyi in Kemper 2211; November 8, 2006.

Ryan, Omar, Mike M., Zhiyi, Mike L., and Bevan near the quad after lunch; August 26, 2004.

Last update: April 29, 2012
Keywords: electrical engineering, computer engineering, university, academic, department, group, lab, laboratory, research development, chip, VLSI, CMOS, circuit, ASIC, FPGA, low power, energy efficient, FFT, DCT, viterbi, FIR, IIR, compression, communication, coding, convolution, correlation, encryption, image, video, JPEG, multimedia, wireless, OFDM, radar, sonor, medical imaging, MRI, magnetic resonance imaging, biological imaging, 802.11a, 802.11g, wireless LAN, transmitter, receiver, H.264 video compresssion encoding decoding, encoder decoder, codec, AES encryption decryption, networks on-chip, on-chip networks, routers, source-synchronous, interconnects, interconnection