People of the VCL

Faculty
	Professor Bevan Baas
Graduate students
	Tinoosh Mohsenin Ph.D. Student LDPC architectures Architectural design Array architecture mappings		Dean Truong Ph.D. Student Architectures High speed chip design AsAP 2.0 physical design
	Zhibin Xiao Ph.D. Student Architectures Video and multimedia applications System design		Paul Mejia Ph.D. Student Software-defined radio architectures High speed low power system design Printed circuit board design
	Anh Tran Ph.D. Student Wireless baseband transmitter/receiver Software Defined Radio platforms High-performance DSP implementation
	Jeremy Webb MS Student High-speed board design System interfacing System integration		Christine Watnik MS Student DSP C compiler backend Viterbi accelerator AsAP code scheduler
	Gouri Landge MS Student H.264 accelerator Video mapping Video processing hardware		Jeff Collins MS Student High-speed board design H.264 application Video processing hardware
	Stephen Le MS Student High-speed simulator Parallel H.264 software Tool integration
Other graduate researchers:
Undergraduate Researchers
Current and recent: Henna Huang Jon Pimentel Kyle Piper
Alumni
	Dr. Zhiyi Yu Ph.D. ECE, Oct. 2007 Hardware Engineer IntellaSys Network on chip GALS clocking AsAP 1.0 physical design
	Ryan Apperson MS ECE, Sept. 2004 IC Design Engineer Boston Scientific, CRM Division Asynchronous data interfacing circuits SRAM design Full-custom CMOS layout		Omar Sattari MS ECE, Sept. 2004 Software Engineer CornerTurn Address generation and branching CAD environment Programming assembler, config FFT algorithm mapping
	Mike Lai MS ECE, Sept. 2004 Design Engineer Altera High-speed pipelined signed multiplier High-speed modular signed adder Full-custom CMOS layout		Mike Meeuwsen MS ECE, April 2005 Hardware Engineer Intel, Digital Enterprise Group 802.11a algorithm mapping Architectural enhancements Instruction set design
	Toney Jacobson MS ECE, July 2007 Law Student University of California, Berkeley Fast Fourier Transform (FFT) architectures Digital system design High-speed FPGA design		Eric Work MS ECE, Sept. 2007 Software Engineer S-Machines Arbitrary task to 2D mesh mapping Software tool flow CAD tools
	Wayne Cheng MS ECE, January 2008 ASIC Design Engineer Uniquify Dynamic voltage supply circuits Dynamic voltage and frequency circuits Transistor-level power simulations
Undergraduate researchers: Chi Chen,   BS ECE, June 2006 Sam Lee,   BS ECE, June 2006 Daniel Gurman,   BS ECE, June 2006 Bassem Saad,   BS ECE, June 2006 Leo Chan,   BS ECE, June 2006 Jason Cheung,   BS CS, June 2005 Tomoko Tsuruta,   BS ECE, June 2005 William Au Yeung,   BS ECE, June 2005

Current Research

Asynchronous Array of simple Processors (AsAP)

Many members of the VCL are participating in work on the circuits, functional units, architecture, interconnection network, algorithms, and applications for a high-performance and energy-efficient processing system targeting computationally-demanding multi-algorithm DSP system applications. The single-chip processing system is comprised of a large number of fine-grain asynchronously-operating programmable processors connected by a reconfigurable 2-dimensional mesh network.

The 0.18 μm AsAP 1 chip contains 36 programmable processors, operates at over 610 MHz at 2.0 V, and is believed to be the highest clock rate processor designed in any university. Details of the chip were presented in the Technology and Architecture Directions session at ISSCC in Feb. 2006. See the paper below.

Also see the EE Times article "Asynchronous array of processors chip presented at ISSCC 2006," February 9, 2006.



Low Density Parity Check (LDPC) Decoders

We are working on LDPC algorithms, architectures, and circuits targeting several regimes, with a continual emphasis on high energy efficiency:
• Very high rate decoders
• Efficient decoding algorithms useful at many throughput rates

Special Purpose Processors

We are working on algorithms, architectures, and circuits for a number of dedicated purpose processing engines. Several active projects include:
• Fast Fourier Transform (FFT)
• Viterbi decoder
• H.264 video encoding and decoding

Sponsors of Our Work

	National Science Foundation   • CAREER award No. 0546907   • CCF Grant No. 0430090		Intel Corporation
	UC MICRO		SRC, Semiconductor Research Corporation   • GRC Grant 1598.001   • CSR Grant 1659.001
	ST Microelectronics		Intellasys Corporation
SEM	SEM		Committee on Research, Faculty Research Grant
	Xilinx Incorporated, Equipment grants		Atheros Communications, Equipment grant

Miscellaneous

Computing resources within the VLSI Computation Lab

Publications in review and in preparation not yet listed.

2008


• Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik,
  Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan Baas,
  "A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling,"
  Symposium on VLSI Circuits, June 2008, to appear.

• Zhiyi Yu and Bevan Baas,
  "High Performance, Energy Efficiency, and Scalability with GALS Chip Multiprocessors,"
  IEEE Transactions of Very Large Scale Integration Systems (TVLSI), in press.

• Zhiyi Yu and Bevan Baas,
  "Low-Area Interconnect Architecture for Chip Multiprocessors,"
  IEEE International Symposium on Circuits and Systems (ISCAS), May 2008, to appear.

• Wayne Cheng and Bevan Baas,
  "Dynamic Voltage and Frequency Scaling Circuits with Two Supply Voltages,"
  IEEE International Symposium on Circuits and Systems (ISCAS), May 2008, to appear.

• Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Tinoosh Mohsenin, Bevan Baas,
  "Architecture and Evaluation of an Asynchronous Array of Simple Processors,"
  Journal of VLSI Signal Processing Systems, March 2008.

• Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Dean Truong, Tinoosh Mohsenin, Bevan Baas,
  "AsAP: An Asynchronous Array of Simple Processors,"
  IEEE Journal of Solid-State Circuits (JSSC), vol. 43, no. 3, pp. 695-705, March 2008.

• Wayne H. Cheng,
  "Approaches and Designs of Dynamic Voltage and Frequency Scaling,"
  Masters Thesis, Technical Report ECE-CE-2008-1, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2008.

  2007
  

• Zhiyi Yu,
  "High Performance and Energy Efficient Multi-core Systems for DSP Applications,"
  Ph.D Dissertation, Technical Report ECE-CE-2007-5, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2007.

• Ryan Apperson, Zhiyi Yu, Michael Meeuwsen, Tinoosh Mohsenin, Bevan Baas,
  "A Scalable Dual-Clock FIFO for Data Transfers between Arbitrary and Haltable Clock Domains,"
  IEEE Transactions of Very Large Scale Integration Systems (TVLSI), vol. 15, no. 10, pp. 1125-1134, October 2007.

• Eric W. Work,
  "Algorithms and Software Tools for Mapping Arbitrarily Connected Tasks onto an Asynchronous Array of Simple Processors,"
  Masters Thesis, Technical Report ECE-CE-2007-4, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2007.

• Anthony T. Jacobson,
  "A Continuous-Flow Mixed-Radix Dynamically-Configurable FFT Processor,"
  Masters Thesis, Technical Report ECE-CE-2007-3, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2007.

• Michael Meeuwsen, Zhiyi Yu, Bevan Baas,
  "A Shared Memory Module for Asynchronous Arrays of Processors,"
  EURASIP Journal on Embedded Systems, vol. 2007, Article ID 86273, 13 pages, 2007.

• Bevan Baas, Zhiyi Yu, Michael Meeuwsen, Omar Sattari, Ryan Apperson, Eric Work, Jeremy Webb, Michael Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung,
  "AsAP: A Fine-grain Multi-core Platform for DSP Applications,"
  IEEE Micro, Volume 27, Number 2, March/April 2007.
  Invited.

• Tinoosh Mohsenin, Bevan M. Baas,
  "High-Throughput LDPC Decoders Using A Multiple Split-Row Method,"
  In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '07), April 2007.

  2006
  

• Zhiyi Yu, Bevan M. Baas,
  "Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles ,"
  In Proceedings of the IEEE International Conference of Computer Design (ICCD '06), October 2006, pp. 174-179.

• Tinoosh Mohsenin, Bevan M. Baas,
  "Split-row: A reduced complexity, high throughput LDPC decoder architecture ,"
  In Proceedings of the IEEE International Conference of Computer Design (ICCD '06), October 2006, pp. 320-325.

• Bevan Baas, Zhiyi Yu, Michael Meeuwsen, Omar Sattari, Ryan Apperson, Eric Work, Jeremy Webb, Michael Lai, Daniel Gurman, Chi Chen, Jason Cheung, Dean Truong, Tinoosh Mohsenin,
  "Hardware and Applications of AsAP: An Asynchronous Array of Simple Processors,"
  In Proceedings of the IEEE HotChips Symposium on High-Performance Chips, (HotChips 2006), August 2006.

• Zhiyi Yu, Bevan M. Baas,
  "Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems,"
  In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI '06), March 2006, pp. 378-384.

• Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Tinoosh Mohsenin, Mandeep Singh, Bevan M. Baas,
  "An Asynchronous Array of Simple Processors for DSP Applications,"
  In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC '06), February 2006, pp. 428-429, 663.

  2005 and prior
  

• Michael J. Meeuwsen,
  "A Shared Memory Module for an Asynchronous Array of Simple Processors,"
  Masters Thesis, Technical Report ECE-CE-2005-2, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2005.

• Bevan M. Baas,
  "A Generalized Cached-FFT Algorithm,"
  In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2005, March 2005, pp. V-89-92.

• Michael J. Meeuwsen, Omar Sattari, and Bevan M. Baas,
  "A Full-Rate Software Implementation of an IEEE 802.11a Compliant Digital Baseband Transmitter,"
  In Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS '04), Oct. 2004.

• Ryan W. Apperson,
  "A Dual-Clock FIFO for the Reliable Transfer of High-Throughput Data Between Unrelated Clock Domains,"
  Masters Thesis, Technical Report ECE-CE-2004-5, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2004.

• Michael A. Lai,
  "Arithmetic Units for a High Performance Digital Signal Processor,"
  Masters Thesis, Technical Report ECE-CE-2004-6, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2004.

• Omar Sattari,
  "Fast Fourier Transforms on a Distributed Digital Signal Processor,"
  Masters Thesis, Technical Report ECE-CE-2004-7, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2004.

• Bevan M. Baas,
  "A Parallel Programmable Energy-Efficient Architecture For Computationally-Intensive DSP Systems,"
  In Signals, Systems and Computers, 2003. Conference Record of the Thirty-Seventh Asilomar Conference on, November 2003.

• Howard CheHao Chang and Bevan M. Baas,
  "Mapping an FIR Filter to a 2-Dimensional Mesh of Processors,"
  Technical Report ECE-CE-2003-1, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2003.

• Programmable DSP processor design
• Parallel DSP algorithms
• Reconfigurable inter-processor networks
• Functional unit and circuit design
• Processor simulation, emulation, and CAD design flow
• New network topologies and Arbitrary Graph Mapping Tools
• Full-custom CMOS design
• Shorter-term projects (possibly for undergraduate students)
  • Re-design and write the AsAP assembler
  • Enahncements to the Portable Parallel-task Linux Simulator
  • Writing various FFTs on AsAP array
  • Chip design CAD tool projects
• A note to interested prospective students

Downloadable CAD Tools Developed in the VCL

• Arbitrary Graph to 2D Mesh Mapping Tool    
• Low overhead parallel-task linux based simulator

VCL-Specific Material

• Directions to the VCL lab
• Some conventions we use in the VCL lab (good etiquette, writing papers, responding to reviewers)
• VLSI & Sig. Processing conferences, Micro Sys News Calendar
• Unix command notes, Unix tutorials

Other CAD Tools We Use

• Some tools installed locally
• Cadence
  • Tool notes
  • NC verilog
  • Virtuoso
  • Diva
  • Dracula
• Synopsys
  • Solvnet
  • VCS 7.0 release notes
  • HSpice
  • NanoSim
• Magic layout tool
  • Magic web site
• Tutorial web pages
  • Cadence, Synopsys, and other tutorials by James Stine at IIT
  • Cadence, NCSU, and various tutorials by xx
  • Cadence university, has reference designs and misc. stuff

Other Useful Links

• IEEE papers
  • JSSC
  • TVLSI
  • TCAS I: Regular papers; Publication statistics
  • TCAS II: Express briefs
• Microprocessors through the ages
• Intl. Tech. Roadmap for Semiconductors (ITRS)
• Microelectronic Sys News
• MOSIS web site
• CVS help file
• Future technology spice decks from UCB's Predictive Technology Model
• Accurel for FIBing, packaging,...
• Agilent used equipment
• AsAP Wikipedia page
• gds2pov, a 3D GDSII visualization tool

Informative References

• LaTeX: Formulas,
• Deep chip's CAD tool review from CAD '04
• Nice VLSI tutorial
• Libraries and CAD flow from Ill Inst of Tech
• Talk by Pat Gelsinger at DAC, June 2004

A few group pictures

Dean, Zhibin and Paul in office-lab; March 27, 2008.

Zhibin, Dean, Anh, Tinoosh, and Paul working on AsAP2 bringup; October 12, 2007.

Tinoosh, Dean, and Zhibin working on AsAP2 bringup; October 11, 2007.

Dean, Zhibin, Anh, Tinoosh, Paul, and Bevan at ECE Grad Student BBQ in Kemper courtyard; October 4, 2007.

Toney, Wayne, Zhibin, Anh, Zhiyi, Tinoosh, Paul, Dean, and Bevan celebrating Toney's and Wayne's graduations at Woodstock's; August 29, 2007.

Tinoosh, Dean, Christine, Wayne, and Zhiyi in Kemper 2211; November 8, 2006.

Ryan, Omar, Mike M., Zhiyi, Mike L., and Bevan near the quad after lunch; August 26, 2004.

Last update: April 29, 2008
Keywords: electrical engineering, computer engineering, university, academic, department, group, lab, laboratory, research development, chip, VLSI, CMOS, circuit, low power, energy efficient, FFT, DCT, viterbi, FIR, IIR, compression, communication, coding, convolution, correlation, encryption, image, video, JPEG, multimedia, wireless, OFDM, radar, sonor, medical imaging, MRI, magnetic resonance imaging, biological imaging, 802.11a, 802.11g, wireless LAN, transmitter, receiver.