Bevan Baas received a B.S. in electronic engineering from California Polytechnic State University, San Luis Obispo in 1987, and M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1990 and 1999 respectively. His doctoral research was in the areas of algorithms, architectures, and circuits for low-power and high-performance computation. A key portion of his dissertation research was the development of the cached-FFT algorithm and the design of a single-chip 1024-point complex FFT processor which utilizes the algorithm. The full-custom chip contains 460,000 transistors, was fabricated in 0.7 μm standard CMOS, and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates 1024-point FFTs 16 times more efficiently than the previously most efficient processor. At a supply voltage of 3.3 V, it operates at a clock speed of 173 MHz, which is 2.6 times higher than the previously fastest [JSSC, March 1999].

From 1987-89, he served as a new product engineer working on the processor for the 955/3000, 855/9000 Jaguar high-end minicomputer in Hewlett Packard's Computer Systems Division, Cupertino, CA. In 1999, he joined Atheros Communications as the second full-time employee after the founders and served as a core member of the team which developed the first IEEE 802.11a (54 Mbps, 5 GHz) Wi-Fi wireless LAN solution. The chipset has been shipping in volume since September of 2001 and for one and a half years was the only shipping 802.11a chipset [ISSCC 2002]. Atheros became a publicly-held company in Feb. of 2004 (formerly NASDAQ: ATHR) and was purchased by Qualcomm for $3.1 Billion in 2011.

In 2003, Dr. Baas joined the Department of Electrical and Computer Engineering at the University of California, Davis as an Assistant Professor, where he currently supervises research for 13 graduate students. In 2008, he became an Associate Professor.

Dr. Baas' research interests are in the algorithms, architectures, arithmetic, circuits, and VLSI design for high-performance, energy-efficient, and area-efficient computation with strong consideration of the challenges and opportunities of future fabrication technologies. He is interested in both programmable and special-purpose processors with an emphasis on DSP workloads. Recent projects include the AsAP (Asynchronous Array of simple Processors) programmable array processor chip, applications, and tools [ISSCC 2006]; Low Density Parity Check (LDPC) decoders; FFT processors; viterbi decoders; and H.264 video codecs. The 0.18 μm AsAP 1 chip contains 36 programmable processors, operates at over 610 MHz at 2.0 V, and is believed to be the second highest clock rate processor designed in any university. His research group recently completed the design and fabrication of a second generation processing platform with 167 1.2 GHz processors in 65 nm CMOS [VLSI Symp 2008] which is believed to be the highest clock rate processor designed in any university. The chip contains 164 programmable processors that can each independently control their supply voltage and clock frequency; three highly-configurable special-purpose processors: Fast Fourier transform (FFT), H.264 video motion estimation, and Viterbi decoder; and three 1.3 GHz 16 KB shared memories.

Dr. Baas also worked at Hughes Aircraft performing mechanical design and radar system design during two internships. Other positions held include: consultant for a variety of technology companies, legal consultant, computer programmer, plasma etcher machine operator, gardener, sandwich and pasta cook, car washer, mechanical assembly worker, newspaper delivery boy, offset printing press operator, taco/burrito cook, door-to-door salesman, dishwasher, and the most enjoyable job ever (except professor): pizza cook.

Dr. Baas was an NSF Fellow from 1990-93 and a NASA Graduate Student Researcher Fellow from 1993-96. He received the National Science Foundation CAREER award in 2006, and the Most Promising Engineer/Scientist Award by AISES in 2006. During the summer of 2006 he was a Visiting Professor in Intel's Circuit Research Lab. Since 2007 he has been an Associate Editor for the IEEE Journal of Solid-State Circuits. He has served and is serving as a member of: the Technical Program Committee of the International Conference on Computer Design (ICCD) in 2007-09; the Program Committee of the IEEE HotChips Symposium on High-Performance Chips in 2009-10; the Technical Program Committee of the IEEE International Symposium on Asynchronous Circuits and Systems in 2010; and the Technical Advisory Board of an early stage technology company. He is a member of Tau Beta Pi, Phi Kappa Phi, Eta Kappa Nu, AISES, and a Senior Member of the IEEE.


B. Baas | VCL | ECE Dept. | UC Davis
January 2010