CV

RESEARCH

My research is focused on ultra low power digital and mixed-signal integrated circuit design with a particular emphasis on building systems which extract energy from their environment and use it to power a variety of analog, digital, and communications subsystems in the context of wireless sensor networks. The typical average power available from energy harvesting is below 1 mW, and I established the Micropower Circuits and Systems Group to address the challenges of designing useful devices within that power constraint. Although our group has numerous projects spanning circuit design and digital system architecture, I summarize four major research endeavors and list related publications below.

Energy Harvesting Power Supplies:

Several energy sources are available to nodes in a wireless sensor network. Our group has mainly focused on mechanical vibration as an energy source and, in collaboration with researchers at UC Berkeley, have examined piezoelectric beam and disk transducers for converting vibration to electrical energy. I recently gave an overview of this work through a seminar at Stanford University. One of the major challenges of using vibration energy is converting the AC output of the transducer to a DC voltage for circuit use while maintaining high efficiency. We published a paper at this year's Power Electronics Specialists Conference describing a nonlinear control mechanism for creating a supply suitable for analog circuits [1]. Solar energy is a complementary power source to mechanical vibration, but highly efficient solar cells require materials which are difficult to integrate on-chip. If, through circuit design, power consumption can be kept in the microwatt range, then it is possible to use an integrated solar cell (basically, a CMOS passive pixel similar to a camera imager pixel) as a power source. We designed and characterized several such devices for their area and power generation efficiency [2]. We also explored the possibility of using on-chip metal wires to form a capacitor for storing the harvested energy, thus taking advantage of a parasitic effect (wire capacitance) which is typically minimized in digital circuit design [2].
  1. N. Guilar, P. Hurst, and R. Amirtharajah,``Analysis of DC-DC Conversion for Energy Harvesting Systems Using a Mixed-Signal Sliding-Mode Controller,'' 38th IEEE Power Electronics Specialists Conference (PESC 07), 17-21 June 2007, pp. 2620-5.
  2. N. Guilar, A. Chen, T. Kleeburg, and R. Amirtharajah, ``Integrated Solar Energy Harvesting and Storage,'' 2006 International Symposium on Low Power Electronics and Design (ISLPED 06), 4-6 October 2006, pp. 20-4.
  3. S. Meninger, J.-O. Mur-Miranda, R. Amirtharajah, A. Chandrakasan, and J. Lang, ``Vibration-to-Electric Energy Conversion,'' IEEE Transactions on VLSI Systems, Vol. 9, No. 1, Feb. 2001, pp. 64-76.
  4. A. Dancy, R. Amirtharajah, and A. Chandrakasan, ``High-Efficiency Multiple-Output DC-DC Conversion for Low-Voltage Systems,'' IEEE Transactions on VLSI Systems, Vol. 8, No. 3, June 2000, pp. 252-63.

Self-Timed Circuits for AC Supply Voltages:

Converting AC voltage to DC voltage is usually inefficient at output power levels below 1 mW, with typical efficiencies reported for vibration-based energy harvesting systems between 18% and 65%. One can eliminate the need for full AC/DC conversion and rely on a simple full-wave rectifier circuit with minimum filtering capacitance by redesigning the load circuits to utilize the AC power supply directly. The key insight is that mechanical vibration frequencies are often so low (60 Hz - 1 kHz), the resulting supply voltages are slowly varying compared to integrated circuit speeds. Thus, self-timed circuit design can be used to implement VLSI systems which do not need DC supplies since the self-timing techniques guarantee correct operation over a wide range of supply voltages. We designed and verified a test chip, published in the 2007 Symposium on VLSI Circuits, which incorporates an on-chip rectifier, fast power-on-reset circuit, self-timing based on a replica ring oscillator, and 3-transistor DRAM cell-based memories [1]. The reset and DRAM are required to initialize pipeline registers on power-up and maintain state across AC power supply cycles, respectively.
  1. J. Wenck, J. Collier, J. Siebert, and R. Amirtharajah, ``AC Power Supply Circuits for Energy Harvesting,'' 2007 Symposium on VLSI Circuits (VLSI 2007), 14-16 June 2007, pp. 92-3.
  2. R. Amirtharajah, J. Collier, J. Siebert, J. Wenck, and B. Zhou, ``Circuits for Energy Harvesting Sensor Signal Processing'' (invited) 2006 43rd ACM/IEEE Design Automation Conference (DAC 06), 24-28 July 2006, pp. 639-44.
  3. J. Siebert, J. Collier, and R. Amirtharajah, ``Self-Timed Circuits for Energy Harvesting AC Power Supplies,'' 2005 International Symposium on Low Power Electronics and Design (ISLPED 05), August 2005, pp. 315-8.

Energy Scalable Architectures for Sensor Signal Processing:

Another critical issue faced by energy harvesting systems is the wide variability of available power. For example, available solar energy can vary by orders of magnitude depending on lighting conditions. Addressing this challenge requires systems to be energy scalable, i.e. the system enables a tradeoff between power consumption and output quality which allows graceful degradation of system performance as less energy becomes available. One elegant way of implementing this tradeoff is to use serial arithmetic structures, which we have shown can offer less total power consumption than parallel structures if leakage is dominant [1]. We are extending these results by building an array of reconfigurable energy scalable functional units which will allow direct implementation of signal processing flow graphs through a reconfigurable interconnect fabric [2, 3]. Minimizing the power consumption of the interconnect is key to decreasing the overall power consumption on-chip; to that end, we are adapting pulse modulation techniques originally developed for off-chip communication [6, 7]. A test chip for experimental verification of these ideas will be completed in summer 2007.
  1. R. Amirtharajah, J. Collier, J. Siebert, J. Wenck, and B. Zhou, ``Circuits for Energy Harvesting Sensor Signal Processing'' (invited) 2006 43rd ACM/IEEE Design Automation Conference (DAC 06), 24-28 July 2006, pp. 639-44.
  2. L. Guo, M. Scott, and R. Amirtharajah, ``An Energy Scalable Functional Unit for Sensor Signal Processing,'' IEEE 2007 International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 15-20 April 2007, Vol. II, pp. 73-6.
  3. L. Guo, M. Scott, and R. Amirtharajah, ``An Energy Scalable Computational Array for Sensor Signal Processing,'' IEEE 2006 Custom Integrated Circuits Conference (CICC), 10-13 September 2006, pp. 317-20.
  4. R. Amirtharajah, ``An Energy Scalable Computational Array for Sensor Signal Processing'' (invited) 2006 ISSCC Special Topic Session on Power-Aware Signal Processing, 5 February 2006.
  5. R. Amirtharajah, J. Collier, J. Siebert, B. Zhou and, A. Chandrakasan, ``DSPs for Energy Harvesting Sensors: Applications and Architectures,'' IEEE Pervasive Computing Magazine, Vol. 4, Issue 3, July-Sep. 2005, pp. 72-9.
  6. R. Amirtharajah and A. Chandrakasan, ``A Micropower Programmable DSP Using Approximate Signal Processing Based on Distributed Arithmetic,'' IEEE Journal of Solid-State Circuits, Vol. 39, No. 2, Feb. 2004, pp. 337-47.
  7. T. Simon, R. Amirtharajah, J.R. Benham, J. Critchlow, and T.F. Knight, Jr., ``A 1.6 Gb/s/pair Electromagnetically Coupled Multidrop Bus Using Modulated Signaling,'' 2003 ISSCC Digest of Technical Papers, Feb. 2003, pp. 184-5, 487.

Low Power Interfaces for Nanomaterial Sensors:

Nanoscale materials such as carbon nanotubes and silicon nanowires offer the exciting prospect of enabling low cost, low power, highly sensitive detectors for a wide variety of chemical and biological materials. Self-assembly of these materials into sensors can achieve low cost at the expense of wide variations in sensor characteristics. Moreover, low power interface circuits such as analog-digital converters are necessary to incorporate these novel devices into energy harvesting wireless sensors. We have analyzed a number of different interfaces and sensor optimization schemes to determine how circuits and reconfigurability can compensate for the variations and tolerate the noise and defects associated with these new materials and nanoscale devices in general.
  1. R. Amirtharajah, A. Chen, D. Thaker, and F. T. Chong, ``Circuit Interfaces and Optimization for Resistive Nanosensors,'' (invited) Proc. of SPIE, Vol. 6008: Nanosensing: Materials and Devices II, 23-26 October 2005, pp. 60080J1-15.
  2. R. Amirtharajah, A. Chen, J. Loo and N. Guilar, ``Nanomaterial Resistive Sensors: Noise, Power, and Circuit Interfaces,'' International Journal of Nanotechnology, to appear.
  3. D. D. Thaker, R. Amirtharajah, F. Impens, I. L. Chuang and, F. T. Chong, ``Recursive TMR: Scaling Fault Tolerance in the Nanoscale Era,'' IEEE Design & Test of Computers, Vol. 22, Issue 4, July-Aug. 2005, pp. 298-305.

TEACHING and ADVISING

Since beginning at UC Davis in 2003, I have advised fourteen graduate students. The four MS students who have graduated work for leading companies such as Intel, Boston Scientific, and Teradyne. Three more MS students who will receive their degrees soon have accepted offers from Cisco and Faraday Technology. I am currently supervising four PhD students and six MS students. I began my teaching career by developing a new graduate course: Low Power Digital Integrated Circuit Design, which is taught yearly as course number EEC 216. The course relies on circuit simulations using Hspice, problem sets, and design projects to teach students how power can be treated as a first class design objective for integrated circuits. Circuit design has traditionally optimized speed over power consumption. This class also offers an introduction to power electronics in the ECE curriculum, so students can gain familiarity with the circuits that deliver power to digital systems. EEC 216 has been well received, with average course evaluations of 9.4/10. I have also taught the introductory graduate analog circuits class, EEC 210 Analog MOS Integrated Circuit Design, based on the Gray, Hurst, Lewis, and Meyer textbook (Average Course Evaluation: 8.6). My core undergraduate class is EEC 118 Digital Integrated Circuits, an upper-division course which focuses on CMOS digital circuit design and culminates in a group design project (Average Course Evaluation: 8.0). In addition, I have taught undergraduate classes E100 Electronic Circuits and Systems and EEC 180A Digital Systems I.

SERVICE

To promote interest in energy scavenging research and microwatt integrated circuit design, I engaged with the research community outside UC Davis by giving seminars at universities such as UC Berkeley, UCLA, CalTech, and Stanford, as well as the IEEE 2005 Vail Computer Elements Workshop. I have spoken about my work to industry engineers at Smart Dust, National Semiconductor Corp., Xilinx, and S3C Corp. I also delivered invited talks at two premier conferences in the field of integrated circuit design: the 2006 IEEE International Solid-State Circuits Conference (ISSCC) and the 2006 ACM/IEEE 43rd Design Automation Conference (DAC). I serve on the Technical Program Committees of several conferences in integrated circuit and sensor design. These include the IEEE International Solid-State Circuits Conference (ISSCC) 2005-present, the IEEE Hot Chips Conference (2006 as a member, 2007 as co-chair), the IEEE Custom Integrated Circuits Conference (CICC) 2007, and the SPIE Nanosensing: Materials and Devices conferences (Optics East 2005-7). As part of the 2005 Optics East conference, I chaired a session entitled Novel Synthesis, Characterization, Assembly, and Integration of Nanostructure Arrays for Sensing II. I organized a special topics evening session as part of the 2006 ISSCC on Power-Aware Signal Processing. In addition, I am chairing sessions for the 2007 Hot Chips and CICC conferences. I serve as a paper reviewer for several distinguished IEEE and ACM journals, including the IEEE Journal of Solid-State Circuits, and have also reviewed a book proposal for the Cambridge University Press. I have been a grant proposal reviewer for the U.S. Dept. of Agriculture, Small Business Innovation Research (SBIR) program and the University of California MICRO program. I also served on a National Science Foundation Panel reviewing proposals for the program on Integrative, Hybrid, and Complex Systems in 2006.

BIOGRAPHY

Rajeevan Amirtharajah received the S.B. and M.Eng. degrees in 1994, and the Ph.D. degree in 1999, all in electrical engineering from the Massachusetts Institute of Technology, Cambridge, MA. His doctoral work developed micropower DSP systems which scavenge energy from mechanical vibrations in their environment and use that energy to process information provided by embedded and wearable sensors. From 1999 to 2002, as a senior member of the technical staff at High Speed Solutions Corp., Hudson, MA, later a subsidiary of Intel Corporation, he helped create innovative high performance multidrop bus technologies using electromagnetic coupling and pulse-based modulated signaling. He worked as an ASIC and mixed-signal circuit design consultant at SMaL Camera Technologies, Cambridge, MA, in 2003. In July 2003, he joined the Electrical and Computer Engineering department at the University of California, Davis, where he is currently an assistant professor. His research interests include low power VLSI design for sensor applications, powering systems from ambient energy sources, and high performance circuit and interconnect design. He received the National Science Foundation CAREER award in 2006. He is an inventor on eighteen United States patents and is a member of IEEE, AAAS, and Sigma Xi.
Last update: July 26, 2007
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©2007, R. Amirtharajah, University of California