[VLSI Computation Lab]

Asynchronous Array of Simple Processors (AsAP) project

"You know you have achieved perfection in design, not when you have nothing more to add, but when you have nothing more to take away"
                                                       - Antoine de Saint-Exupéry

"People who are really serious about software should make their own hardware"
                                - Alan Kay

Members of the VCL are currently focused on the circuits, functional units, architecture, interconnection network, algorithms, applications, and chip design for a high-performance and energy-efficient processing system targeting computationally-demanding applications. The single-chip processing system is comprised of a large number of fine-grain asynchronously-operating programmable processors connected by a reconfigurable network.

We have designed 36-processor and 167-processor chips that have been fabricated and found to be fully functional. We believe they are among the highest clock rate fabricated processors designed in any university--in fact, we believe the 167-core chip is the fastest.

Details of the chips and applications were presented at/in: ISSCC, ISVLSI, HotChips, ICCD, IEEE MICRO, EURASIP, IEEE TVLSI, IEEE JSSC, ISCAS, Symp on VLSI Circuits, and many other venues. A complete list of publications can be found at: www.ece.ucdavis.edu/vcl/#Publications.

Target Applications

Project Objectives
  1. High energy efficiency (at all times)
  2. High performance (capable of)
  3. Small circuit area (relatively)
  4. Easy to program (relatively)
  5. Well suited for future fabrication technologies
Key features

AsAP 1 chip (36 processors)


The first generation AsAP processor contains 36 identical processors with independent clock domains. Each processor is a reduced complexity programmable DSP with small memories, which can dramatically increase system area efficiency and energy efficiency. Each processor can receive data from any two neighbors and send data to any of its four neighbors. The block diagram of AsAP processor is shown below.

Below is a photo micrograph of the fully-functional single-chip 36-core AsAP processor array.


Chip design

We used a number of CAD tools from Cadence and Synopsys for our chip design. This page contains an overview of our CAD tool flow including progress and issues. Here are some topics and issues we considered before the tape out.

Test board

The AsAP test board is the custom-designed printed circuit board shown on the right and is designed to work with a commercial Memec FPGA board shown on the left.


Several DSP tasks and applications such as FFT, JPEG core encoder and 802.11a/802.11g wireless transmitter are mapped onto AsAP processor. 802.11a/802.11g implementation using 22 processors is shown below. It consumes 407 mW at 300 MHz and achieve 30% of 54 Mb/s performance. These results are around 10 times higher performance and 35x - 75x lower energy dissipation than 8-way VLIW TI C62x (according one implementation reported at ICC02).

Results (First Generation)

AsAP processor operates at 475 MHz; and each processor dissipates 32 mW while executing applications, 84 mW while 100% active, and 144 mW worst-case at 1.8 V. Most of AsAP's area (66%) is for the core which is a high area utilization. Each processor occupies 0.66 mm2, which is more than 20 times smaller than the other traditional processors such as ARM. AsAP processor also achieves more than 5 times higher performance density and energy efficiency compared with others, as shown at below.

AsAP 2 chip (167 processors)

Key features

Below is the die micrograph of the fully-functional single-chip 167-processor AsAPs2 array processor.

Key data

Development boards

Work has begun on two development boards: one for high-speed AsAP array emulation on an FPGA, and the other to host our planned CMOS chip. Key features for both boards include: Information on the AsAP version 1 development board can be found at: http://www.ece.ucdavis.edu/vcl/asap/asap_v1/asap_ver1.shtml.

Measurements and Characterization

Here is our checklist of things to measure and characterize in the AsAP1 and AsAP2 chips.


This material is based upon work supported by Intel Corporation, UC MICRO, the National Science Foundation under Grant No. 0430090 and CAREER grant No. 0546907, and a UCD Faculty Research Grant. Any opinions, findings and conclusions or recomendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation (NSF).

VCL | ECE Dept. | UC Davis

Last update: April 12, 2013
Keywords: many-core, multi-core, array processor, homogenous, heterogeneous, NoC, network on chip, interconnect, mesh, GALS, globally asynchronous locally synchronous, electrical engineering, computer engineering, university, academic, department, group, lab, laboratory, research development, chip, VLSI, CMOS, circuit, low power, energy efficient, FFT, DCT, viterbi, FIR, IIR, compression, communication, coding, convolution, correlation, encryption, image, video, JPEG, multimedia, wireless, OFDM, radar, sonor, medical imaging, MRI, magnetic resonance imaging, biological imaging, 802.11a, 802.11g, wireless LAN, transmitter, receiver.

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