A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling

Abstract:

A 167-processor 65 nm computational platform well suited for DSP, communication, and multimedia workloads contains 164 programmable processors with dynamic supply voltage and dynamic clock frequency circuits, three algorithm-specific processors, and three 16 KB shared memories, all clocked by independent oscillators and connected by configurable long-distance-capable links.

Paper

  PDF (240 KB),   (c) Copyright, 2008 IEEE

Presentation Slides

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Reference

Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan M. Baas. "A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling." Symposium on VLSI Circuits, (VLSI '08), June 2008, pp. 22-23.

BibTeX entry

@inproceedings{UCDVCL:2008:VLSI,
   author    = {Dean Truong and Wayne Cheng and Tinoosh Mohsenin and
                Zhiyi Yu and Toney Jacobson and Gouri Landge and 
		Michael Meeuwsen and Christine Watnik and Paul Mejia and
		Anh Tran and Jeremy Webb and Eric Work and Zhibin Xiao and
                Bevan M. Baas},
   title     = {A 167-processor 65 nm Computational Platform with Per-Processor
                Dynamic Supply Voltage and Dynamic Clock Frequency Scaling},
   booktitle = {Symposium on VLSI Circuits, (VLSI '08)},
   month     = jun,
   year      = 2008,
   pages     = {22-23}
   }

Last update: June 11, 2008