A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling

Dean Truong
Wayne Cheng
Tinoosh Mohsenin
Zhiyi Yu
Toney Jacobson
Gouri Landge
Michael Meeuwsen
Christine Watnik
Paul Mejia
Anh Tran
Jeremy Webb
Eric Work
Zhibin Xiao
Bevan Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Abstract:

A 167-processor 65 nm computational platform well suited for DSP,
communication, and multimedia workloads contains 164 programmable 
processors with dynamic supply voltage and dynamic clock frequency 
circuits, three algorithm-specific processors, and three 16 KB 
shared memories, all clocked by independent oscillators and
connected by configurable long-distance-capable links. 

Paper

Presentation Slides

Reference

Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan M. Baas. "A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling." Symposium on VLSI Circuits, (VLSI '08), June 2008, pp. 22-23.

BibTeX Entry

@INPROCEEDINGS{Truong:VLSISymp,
    author={Truong, D. and Cheng, W. and Mohsenin, T. and Zhiyi Yu and Jacobson, T. and 
            Landge, G. and Meeuwsen, M. and Watnik, C. and Mejia, P. and Anh Tran and 
            Webb, J. and Work, E. and Zhibin Xiao and Baas, B.},
    booktitle={VLSI Circuits, 2008 IEEE Symposium on}, 
    title={A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling},
    year={2008},
    month={Jun.},
    doi={10.1109/VLSIC.2008.4585936}
}

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Last update: Sep. 27, 2010